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/linux/Documentation/translations/zh_CN/driver-api/phy/
H A Dphy.rst16 本文档解释了 PHY 的通用框架和提供的API，以及使用方法。
21 *PHY* 是物理层的缩写，它被用来把设备连接到一个物理媒介，例如USB控制器
22 有一个提供序列化、反序列化、编码、解码和负责获取所需的数据传输速率的 PHY。
23 注意，有些USB控制器内嵌了 PHY 的功能，其它的则使用了一个外置的PHY，此外
24 使用 PHY 的设备还有无线网、以太网、SATA等（控制器）。
26 创建这个框架的目的是将遍布 Linux 内核的 PHY 驱动程序融入到 drivers/phy，
29 该框架仅适用于使用外部 PHY（PHY 功能未嵌入控制器内）的设备。
34 PHY provider是指实现一个或多个 PHY 实例的实
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/linux/drivers/gpu/drm/ci/xfails/
H A Di915-glk-skips.txt80 # i915 0000:00:02.0: [drm] *ERROR* AUX A/DDI A/PHY A: not done (status 0x00000000)
81 # i915 0000:00:02.0: [drm] *ERROR* AUX A/DDI A/PHY A: not done (status 0x00000000)
82 # i915 0000:00:02.0: [drm] *ERROR* AUX A/DDI A/PHY A: not done (status 0x00000000)
83 # i915 0000:00:02.0: [drm] *ERROR* AUX A/DDI A/PHY A: not done (status 0x00000000)
84 # i915 0000:00:02.0: [drm] *ERROR* AUX A/DDI A/PHY A: not done (status 0x00000000)
85 # i915 0000:00:02.0: [drm] *ERROR* AUX A/DDI A/PHY A: not done (status 0x00000000)
86 # i915 0000:00:02.0: [drm] *ERROR* AUX A/DDI A/PHY A: not done (status 0x00000000)
87 # i915 0000:00:02.0: [drm] *ERROR* AUX A/DDI A/PHY A: not done (status 0x00000000)
88 # i915 0000:00:02.0: [drm] *ERROR* AUX A/DDI A/PHY A: not done (status 0x00000000)
89 # i915 0000:00:02.0: [drm] *ERROR* AUX A/DDI A/PHY
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/linux/Documentation/driver-api/phy/
H A Dphy.rst2 PHY subsystem
7 This document explains the Generic PHY Framework along with the APIs provided,
13 *PHY* is the abbreviation for physical layer. It is used to connect a device
14 to the physical medium e.g., the USB controller has a PHY to provide functions
17 controllers have PHY functionality embedded into it and others use an external
18 PHY. Other peripherals that use PHY include Wireless LAN, Ethernet,
21 The intention of creating this framework is to bring the PHY drivers spread
25 This framework will be of use only to devices that use external PHY (PHY
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/linux/drivers/phy/qualcomm/
H A DKconfig6 tristate "Atheros AR71XX/9XXX USB PHY driver"
12 Enable this to support the USB PHY on Atheros AR71XX/9XXX SoCs.
15 tristate "Qualcomm APQ8064 SATA SerDes/PHY driver"
22 tristate "Qualcomm eDP PHY driver"
28 Enable this driver to support the Qualcomm eDP PHY found in various
32 tristate "Qualcomm IPQ4019 USB PHY driver"
36 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
39 tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
46 tristate "Qualcomm PCIe Gen2 PHY Driver"
50 Enable this to support the Qualcomm PCIe PHY, use
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/linux/drivers/phy/broadcom/
H A DKconfig5 menu "PHY drivers for Broadcom platforms"
8 tristate "BCM63xx USBH PHY driver"
12 Enable this to support the BCM63xx USBH PHY driver.
16 tristate "Broadcom Cygnus PCIe PHY driver"
21 Enable this to support the Broadcom Cygnus PCIe PHY.
25 tristate "Broadcom Stingray USB PHY driver"
30 Enable this to support the Broadcom Stingray USB PHY
36 tristate "Broadcom Kona USB2 PHY Driver"
40 Enable this to support the Broadcom Kona USB 2.0 PHY.
43 tristate "Broadcom Northstar USB 2.0 PHY Drive
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/linux/drivers/phy/ti/
H A DKconfig6 tristate "TI DA8xx USB PHY Driver"
11 Enable this to support the USB PHY on DA8xx SoCs.
13 This driver controls both the USB 1.1 PHY and the USB 2.0 PHY.
16 tristate "TI dm816x USB PHY driver"
33 This option enables support for TI AM654 SerDes PHY used for
53 tristate "OMAP CONTROL PHY Driver"
56 Enable this to add support for the PHY part present in the control
57 module. This driver has API to power on the USB2 PHY and to write to
59 power on the USB2 PHY i
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/linux/drivers/phy/rockchip/
H A DKconfig6 tristate "Rockchip Display Port PHY Driver"
10 Enable this to support the Rockchip Display Port PHY.
25 tristate "Rockchip EMMC PHY Driver"
29 Enable this to support the Rockchip EMMC PHY.
32 tristate "Rockchip INNO HDMI PHY Driver"
38 Enable this to support the Rockchip Innosilicon HDMI PHY.
49 Support for Rockchip USB2.0 PHY with Innosilicon IP block.
52 tristate "Rockchip Innosilicon MIPI CSI PHY driver"
57 Enable this to support the Rockchip MIPI CSI PHY with
61 tristate "Rockchip Innosilicon MIPI/LVDS/TTL PHY drive
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/linux/drivers/net/phy/
H A DKconfig3 # PHY Layer Configuration
11 PHYlink models the link between the PHY and MAC, allowing fixed
16 tristate "PHY Device support and infrastructure"
19 Ethernet controllers are usually attached to PHY
21 managing PHY devices.
35 Adds support for a set of LED trigger events per-PHY. Link
38 supported by the PHY and also a one common "link" trigger as a
45 for any speed known to the PHY.
58 tristate "MDIO Bus/PHY emulation with fixed speed/link PHYs"
71 Adds support needed for PHY driver
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/linux/drivers/phy/
H A DKconfig3 # PHY
6 menu "PHY Subsystem"
9 bool "PHY Core"
11 Generic PHY support.
13 This framework is designed to provide a generic interface for PHY
15 API by which phy drivers can create PHY using the phy framework and
16 phy users can obtain reference to the PHY. All the users of this
23 Generic MIPI D-PHY support.
25 Provides a number of helpers a core functions for MIPI D-PHY
29 tristate "NXP LPC18xx/43xx SoC USB OTG PHY drive
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/linux/drivers/phy/cadence/
H A DKconfig7 tristate "Cadence Torrent PHY driver"
13 Support for Cadence Torrent PHY.
16 tristate "Cadence D-PHY Support"
21 Choose this option if you have a Cadence D-PHY in your
26 tristate "Cadence D-PHY Rx Support"
31 Support for Cadence D-PHY in Rx configuration.
34 tristate "Cadence Sierra PHY Driver"
39 Enable this to support the Cadence Sierra PHY driver
42 tristate "Cadence Salvo PHY Driver"
46 Enable this to support the Cadence SALVO PHY drive
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/linux/net/mac80211/
H A Ddebugfs_sta.c805 "PHY CAP: %#.2x %#.2x %#.2x %#.2x %#.2x %#.2x %#.2x %#.2x %#.2x %#.2x %#.2x\n", in link_sta_he_capa_read()
809 PFLAG(PHY, 0, CHANNEL_WIDTH_SET_40MHZ_IN_2G, in link_sta_he_capa_read()
811 PFLAG(PHY, 0, CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G, in link_sta_he_capa_read()
813 PFLAG(PHY, 0, CHANNEL_WIDTH_SET_160MHZ_IN_5G, in link_sta_he_capa_read()
815 PFLAG(PHY, 0, CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G, in link_sta_he_capa_read()
817 PFLAG(PHY, 0, CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G, in link_sta_he_capa_read()
819 PFLAG(PHY, 0, CHANNEL_WIDTH_SET_RU_MAPPING_IN_5G, in link_sta_he_capa_read()
837 PFLAG(PHY, 1, DEVICE_CLASS_A, in link_sta_he_capa_read()
838 "IEEE80211-HE-PHY-CAP1-DEVICE-CLASS-A"); in link_sta_he_capa_read()
839 PFLAG(PHY, in link_sta_he_capa_read()
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/linux/drivers/phy/mediatek/
H A DKconfig6 tristate "MediaTek PCIe-PHY Driver"
11 Say 'Y' here to add support for MediaTek PCIe PHY driver.
12 This driver create the basic PHY instance and provides initialize
17 tristate "MediaTek 10GE SerDes XFI T-PHY driver"
22 Say 'Y' here to add support for MediaTek XFI T-PHY driver.
23 The driver provides access to the Ethernet SerDes T-PHY supporting
28 tristate "MediaTek T-PHY Driver"
34 Say 'Y' here to add support for MediaTek T-PHY driver,
36 SATA, and meanwhile supports two version T-PHY which have
37 different banks layout, the T-PHY wit
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/linux/drivers/phy/marvell/
H A DKconfig6 bool "Armada 375 USB cluster PHY support" if COMPILE_TEST
12 tristate "Marvell Berlin SATA PHY driver"
17 Enable this to support the SATA PHY on Marvell Berlin SoCs.
20 tristate "Marvell Berlin USB PHY Driver"
25 Enable this to support the USB PHY on Marvell Berlin SoCs.
46 Enable this to support Marvell A3700 UTMI PHY driver.
76 Enable this to support Marvell CP110 UTMI PHY driver.
85 tristate "Marvell USB HSIC 28nm PHY Driver"
89 Enable this to support Marvell USB HSIC PHY driver for Marvell
90 SoC. This driver will do the PHY initializatio
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/linux/drivers/phy/socionext/
H A DKconfig3 # PHY drivers for Socionext platforms.
7 tristate "UniPhier USB2 PHY driver"
13 Enable this to support USB PHY implemented on USB2 controller
15 with USB 2.0 PHY that is part of the UniPhier SoC.
16 In case of Pro4, it is necessary to specify this USB2 PHY instead
17 of USB3 HS-PHY.
20 tristate "UniPhier USB3 PHY driver"
25 Enable this to support USB PHY implemented in USB3 controller
29 tristate "Uniphier PHY driver for PCIe controller"
35 Enable this to support PHY implemente
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/linux/drivers/phy/samsung/
H A DKconfig6 tristate "Exynos SoC series Display Port PHY driver"
12 Support for Display Port PHY found on Samsung Exynos SoCs.
15 tristate "S5P/Exynos SoC series MIPI CSI-2/DSI PHY driver"
25 bool "Exynos PCIe PHY driver"
29 Enable PCIe PHY support for Exynos SoC series.
30 This driver provides PHY interface for Exynos PCIe controller.
33 tristate "Exynos SoC series UFS PHY driver"
38 Enable this to support the Samsung Exynos SoC UFS PHY driver for
40 controller to do PHY related programming.
43 tristate "S5P/Exynos SoC series USB 2.0 PHY drive
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/linux/drivers/phy/freescale/
H A DKconfig6 tristate "Freescale i.MX8M USB3 PHY"
13 tristate "Mixel LVDS PHY support"
18 Enable this to add support for the Mixel LVDS PHY as found
22 tristate "Mixel MIPI DSI PHY support"
28 Enable this to add support for the Mixel DSI PHY as found
32 tristate "Freescale i.MX8M PCIE PHY"
36 Enable this to add support for the PCIE PHY as found on
40 tristate "Freescale i.MX8QM HSIO PHY"
44 Enable this to add support for the HSIO PHY as found on
48 tristate "Samsung HDMI PHY suppor
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/linux/Documentation/devicetree/bindings/phy/
H A Dphy-bindings.txt2 information about PHY subsystem refer to Documentation/driver-api/phy/phy.rst
4 PHY device node
8 #phy-cells: Number of cells in a PHY specifier; The meaning of all those
9 cells is defined by the binding for the phy node. The PHY
11 PHY.
14 phy-supply: Phandle to a regulator that provides power to the PHY. This
15 regulator will be managed during the PHY power on/off sequence.
29 That node describes an IP block (PHY provider) that implements 2 different PHYs.
33 PHY user node
37 phys : the phandle for the PHY devic
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/linux/drivers/phy/hisilicon/
H A DKconfig6 tristate "hi6220 USB PHY support"
12 Enable this to support the HISILICON HI6220 USB PHY.
17 tristate "hi3660 USB PHY support"
22 Enable this to support the HISILICON HI3660 USB PHY.
27 tristate "hi3670 USB PHY support"
32 Enable this to support the HISILICON HI3670 USB PHY.
37 tristate "hi3670 PCIe PHY support"
42 Enable this to support the HiSilicon hi3670 PCIe PHY.
56 tristate "HiSilicon INNO USB2 PHY support"
61 Support for INNO USB2 PHY o
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/linux/Documentation/networking/
H A Dphy.rst2 PHY Abstraction Layer
10 PHY. The PHY concerns itself with negotiating link parameters with the link
17 the PHY management code with the network driver. This has resulted in large
23 accessed are, in fact, busses, the PHY Abstraction Layer treats them as such.
30 Basically, this layer is meant to provide an interface to PHY devices which
37 Most network devices are connected to a PHY by means of a management bus.
47 mii_id is the address on the bus for the PHY, and regnum is the register
75 between the clock line (RXC or TXC) and the data lines to let the PHY (clock
77 PHY librar
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H A Dphy-link-topology.rst5 PHY link topology
11 The PHY link topology representation in the networking stack aims at representing
21 | MAC | ------ | PHY | ---- | Port | ---... to LP
25 Commands that needs to configure the PHY will go through the net_device.phydev
26 field to reach the PHY and perform the relevant configuration.
41 Knowing that some modules embed a PHY, the actual link is more like ::
44 | MAC | -------- | PHY (on SFP) |
47 In this case, the SFP PHY is handled by phylib, and registered by phylink through
56 | MAC | ------- | PHY (media converter) | ------- | PHY (o
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H A Doa-tc6-framework.rst4 OPEN Alliance 10BASE-T1x MAC-PHY Serial Interface (TC6) Framework Support
12 PHY supporting full duplex point-to-point operation over 1 km of single
14 PHY supporting full / half duplex point-to-point operation over 15 m of
21 works in conjunction with the 10BASE-T1S PHY operating in multidrop mode.
29 The MAC-PHY solution integrates an IEEE Clause 4 MAC and a 10BASE-T1x PHY
38 The MAC-PHY is specified to carry both data (Ethernet frames) and control
54 low to the MAC-PHY and ends with the deassertion of CSn high. In between
78 10BASE-T1x MAC-PHY Serial Interface Specification,
88 | | | MAC-PHY |
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/linux/drivers/phy/renesas/
H A DKconfig14 tristate "Renesas R-Car generation 2 USB PHY driver"
18 Support for USB PHY found on Renesas R-Car generation 2 SoCs.
21 tristate "Renesas R-Car generation 3 PCIe PHY driver"
25 Support for the PCIe PHY found on Renesas R-Car generation 3 SoCs.
28 tristate "Renesas R-Car generation 3 USB 2.0 PHY driver"
35 Support for USB 2.0 PHY found on Renesas R-Car generation 3 SoCs.
38 tristate "Renesas R-Car generation 3 USB 3.0 PHY driver"
42 Support for USB 3.0 PHY found on Renesas R-Car generation 3 SoCs.
/linux/Documentation/ABI/testing/
H A Dsysfs-class-net-phydev6 Symbolic link to the network device this PHY device is
14 This attribute contains the boolean value whether a given PHY
17 PHY configurations.
24 This attribute contains the 32-bit PHY Identifier as reported
34 This attribute contains the 32-bit PHY Identifier as reported
44 This attribute contains the PHY interface as configured by the
47 appropriate mode for its data lines to the PHY hardware.
61 Boolean value indicating whether the PHY device is used in
71 configuration bits passed from the consumer of the PHY
72 (Ethernet MAC, switch, etc.) to the PHY drive
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/linux/Documentation/devicetree/bindings/net/
H A Dmicrel.txt1 Micrel PHY properties.
21 See the respective PHY datasheet for the mode values.
29 Note that this option in only needed for certain PHY revisions with a
40 - micrel,fiber-mode: If present the PHY is configured to operate in fiber mode
43 by the FXEN boot strapping pin. It can't be determined from the PHY
44 registers whether the PHY is in fiber mode, so this boolean device tree
47 In fiber mode, auto-negotiation is disabled and the PHY can only work in
51 PHY is probed.
53 Some PHYs have a COMA mode input pin which puts the PHY into
/linux/Documentation/networking/device_drivers/ethernet/davicom/
H A Ddm9000.rst94 device, whether or not an external PHY is attached to the device and
113 The chip is connected to an external PHY.
122 Switch to using the simpler PHY polling method which does not
123 try and read the MII PHY state regularly. This is only available
124 when using the internal PHY. See the section on link state polling
128 "Force simple NSR based PHY polling" allows this flag to be
132 PHY Link state polling
137 depending on the version of the chip and on which PHY is being used.
139 For the internal PHY, the original (and currently default) method is
144 To reduce the overhead for the internal PHY, ther
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