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Searched refs:radeon_get_ib_value (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Devergreen_cs.c765 texdw[0] = radeon_get_ib_value(p, idx + 0); in evergreen_cs_track_validate_texture()
766 texdw[1] = radeon_get_ib_value(p, idx + 1); in evergreen_cs_track_validate_texture()
767 texdw[2] = radeon_get_ib_value(p, idx + 2); in evergreen_cs_track_validate_texture()
768 texdw[3] = radeon_get_ib_value(p, idx + 3); in evergreen_cs_track_validate_texture()
769 texdw[4] = radeon_get_ib_value(p, idx + 4); in evergreen_cs_track_validate_texture()
770 texdw[5] = radeon_get_ib_value(p, idx + 5); in evergreen_cs_track_validate_texture()
771 texdw[6] = radeon_get_ib_value(p, idx + 6); in evergreen_cs_track_validate_texture()
772 texdw[7] = radeon_get_ib_value(p, idx + 7); in evergreen_cs_track_validate_texture()
1133 /*tmp =radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1153 track->db_depth_control = radeon_get_ib_value( in evergreen_cs_handle_reg()
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H A Dr600_cs.c848 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1); in r600_cs_common_vline_parse()
864 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != vline_status[0]) { in r600_cs_common_vline_parse()
869 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != RADEON_VLINE_STAT) { in r600_cs_common_vline_parse()
883 header = radeon_get_ib_value(p, h_idx); in r600_cs_common_vline_parse()
884 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1); in r600_cs_common_vline_parse()
1005 /*tmp =radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1023 track->sq_config = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1026 track->db_depth_control = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1038 track->db_depth_info = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1049 track->db_depth_info = radeon_get_ib_value( in r600_cs_check_reg()
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H A Dradeon_vce.c478 offset = radeon_get_ib_value(p, lo); in radeon_vce_cs_reloc()
479 idx = radeon_get_ib_value(p, hi); in radeon_vce_cs_reloc()
565 uint32_t len = radeon_get_ib_value(p, p->idx); in radeon_vce_cs_parse()
566 uint32_t cmd = radeon_get_ib_value(p, p->idx + 1); in radeon_vce_cs_parse()
582 handle = radeon_get_ib_value(p, p->idx + 2); in radeon_vce_cs_parse()
601 *size = radeon_get_ib_value(p, p->idx + 8) * in radeon_vce_cs_parse()
602 radeon_get_ib_value(p, p->idx + 10) * in radeon_vce_cs_parse()
638 tmp = radeon_get_ib_value(p, p->idx + 4); in radeon_vce_cs_parse()
H A Dr300.c641 idx_value = radeon_get_ib_value(p, idx); in r300_packet0_check()
1198 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); in r300_packet3_check()
1209 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { in r300_packet3_check()
1213 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); in r300_packet3_check()
1224 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { in r300_packet3_check()
1228 track->vap_vf_cntl = radeon_get_ib_value(p, idx); in r300_packet3_check()
1236 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); in r300_packet3_check()
1243 track->vap_vf_cntl = radeon_get_ib_value(p, idx); in r300_packet3_check()
1250 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); in r300_packet3_check()
1257 track->vap_vf_cntl = radeon_get_ib_value( in r300_packet3_check()
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H A Dr100.c1307 value = radeon_get_ib_value(p, idx); in r100_reloc_pitch_offset()
1343 c = radeon_get_ib_value(p, idx++) & 0x1F; in r100_packet3_load_vbpntr()
1359 idx_value = radeon_get_ib_value(p, idx); in r100_packet3_load_vbpntr()
1360 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); in r100_packet3_load_vbpntr()
1372 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset); in r100_packet3_load_vbpntr()
1385 idx_value = radeon_get_ib_value(p, idx); in r100_packet3_load_vbpntr()
1386 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); in r100_packet3_load_vbpntr()
1477 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) { in r100_cs_packet_parse_vline()
1491 header = radeon_get_ib_value(p, h_idx); in r100_cs_packet_parse_vline()
1492 crtc_id = radeon_get_ib_value( in r100_cs_packet_parse_vline()
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H A Dradeon_cs.c756 header = radeon_get_ib_value(p, idx); in radeon_cs_packet_parse()
792 printk("\t0x%08x <---\n", radeon_get_ib_value(p, i)); in radeon_cs_packet_parse()
794 printk("\t0x%08x\n", radeon_get_ib_value(p, i)); in radeon_cs_packet_parse()
875 idx = radeon_get_ib_value(p, p3reloc.idx + 1); in radeon_cs_packet_next_reloc()
H A Dradeon_uvd.c572 offset = radeon_get_ib_value(p, data0); in radeon_uvd_cs_reloc()
573 idx = radeon_get_ib_value(p, data1); in radeon_uvd_cs_reloc()
588 cmd = radeon_get_ib_value(p, p->idx) >> 1; in radeon_uvd_cs_reloc()
H A Dr200.c161 idx_value = radeon_get_ib_value(p, idx); in r200_packet0_check()
H A Dradeon.h1047 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) in radeon_get_ib_value() function