Lines Matching refs:radeon_get_ib_value
848 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
864 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != vline_status[0]) {
869 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != RADEON_VLINE_STAT) {
883 header = radeon_get_ib_value(p, h_idx);
884 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
1005 /*tmp =radeon_get_ib_value(p, idx);
1023 track->sq_config = radeon_get_ib_value(p, idx);
1026 track->db_depth_control = radeon_get_ib_value(p, idx);
1038 track->db_depth_info = radeon_get_ib_value(p, idx);
1049 track->db_depth_info = radeon_get_ib_value(p, idx);
1054 track->db_depth_view = radeon_get_ib_value(p, idx);
1058 track->db_depth_size = radeon_get_ib_value(p, idx);
1063 track->vgt_strmout_en = radeon_get_ib_value(p, idx);
1067 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx);
1081 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1093 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
1106 track->cb_target_mask = radeon_get_ib_value(p, idx);
1110 track->cb_shader_mask = radeon_get_ib_value(p, idx);
1113 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));
1119 tmp = G_028808_SPECIAL_OP(radeon_get_ib_value(p, idx));
1139 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1149 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1162 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
1174 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);
1258 track->cb_color_mask[tmp] = radeon_get_ib_value(p, idx);
1278 track->cb_color_bo_offset[tmp] = (u64)radeon_get_ib_value(p, idx) << 8;
1292 track->db_offset = radeon_get_ib_value(p, idx) << 8;
1305 track->htile_offset = (u64)radeon_get_ib_value(p, idx) << 8;
1311 track->htile_surface = radeon_get_ib_value(p, idx);
1387 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;
1494 word0 = radeon_get_ib_value(p, idx + 0);
1501 word1 = radeon_get_ib_value(p, idx + 1);
1502 word2 = radeon_get_ib_value(p, idx + 2) << 8;
1503 word3 = radeon_get_ib_value(p, idx + 3) << 8;
1504 word4 = radeon_get_ib_value(p, idx + 4);
1505 word5 = radeon_get_ib_value(p, idx + 5);
1641 idx_value = radeon_get_ib_value(p, idx);
1655 tmp = radeon_get_ib_value(p, idx + 1);
1716 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
1767 (radeon_get_ib_value(p, idx+1) & 0xfffffff0) +
1768 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1785 command = radeon_get_ib_value(p, idx+4);
1803 tmp = radeon_get_ib_value(p, idx) +
1804 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
1833 tmp = radeon_get_ib_value(p, idx+2) +
1834 ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32);
1855 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
1856 radeon_get_ib_value(p, idx + 2) != 0) {
1879 (radeon_get_ib_value(p, idx+1) & 0xfffffff8) +
1880 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1901 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
1902 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1957 switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) {
1983 base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2),
1984 mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3),
2000 offset = radeon_get_ib_value(p, idx+1+(i*7)+0);
2001 size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1;
2107 offset = (u64)radeon_get_ib_value(p, idx+1) << 8;
2145 offset = radeon_get_ib_value(p, idx+1);
2146 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2164 offset = radeon_get_ib_value(p, idx+3);
2165 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2189 offset = radeon_get_ib_value(p, idx+0);
2190 offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL;
2218 offset = radeon_get_ib_value(p, idx+1);
2219 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2230 reg = radeon_get_ib_value(p, idx+1) << 2;
2242 offset = radeon_get_ib_value(p, idx+3);
2243 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2254 reg = radeon_get_ib_value(p, idx+3) << 2;
2393 header = radeon_get_ib_value(p, idx);
2406 dst_offset = radeon_get_ib_value(p, idx+1);
2412 dst_offset = radeon_get_ib_value(p, idx+1);
2413 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2437 idx_value = radeon_get_ib_value(p, idx + 2);
2441 src_offset = radeon_get_ib_value(p, idx+1);
2445 dst_offset = radeon_get_ib_value(p, idx+5);
2446 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;
2451 src_offset = radeon_get_ib_value(p, idx+5);
2452 src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;
2456 dst_offset = radeon_get_ib_value(p, idx+1);
2463 src_offset = radeon_get_ib_value(p, idx+2);
2464 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2465 dst_offset = radeon_get_ib_value(p, idx+1);
2466 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;
2474 src_offset = radeon_get_ib_value(p, idx+2);
2475 src_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;
2476 dst_offset = radeon_get_ib_value(p, idx+1);
2477 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff0000)) << 16;
2507 dst_offset = radeon_get_ib_value(p, idx+1);
2508 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16;