Lines Matching refs:radeon_get_ib_value
765 texdw[0] = radeon_get_ib_value(p, idx + 0);
766 texdw[1] = radeon_get_ib_value(p, idx + 1);
767 texdw[2] = radeon_get_ib_value(p, idx + 2);
768 texdw[3] = radeon_get_ib_value(p, idx + 3);
769 texdw[4] = radeon_get_ib_value(p, idx + 4);
770 texdw[5] = radeon_get_ib_value(p, idx + 5);
771 texdw[6] = radeon_get_ib_value(p, idx + 6);
772 texdw[7] = radeon_get_ib_value(p, idx + 7);
1133 /*tmp =radeon_get_ib_value(p, idx);
1153 track->db_depth_control = radeon_get_ib_value(p, idx);
1171 track->db_z_info = radeon_get_ib_value(p, idx);
1199 track->db_s_info = radeon_get_ib_value(p, idx);
1203 track->db_depth_view = radeon_get_ib_value(p, idx);
1207 track->db_depth_size = radeon_get_ib_value(p, idx);
1211 track->db_depth_slice = radeon_get_ib_value(p, idx);
1221 track->db_z_read_offset = radeon_get_ib_value(p, idx);
1233 track->db_z_write_offset = radeon_get_ib_value(p, idx);
1245 track->db_s_read_offset = radeon_get_ib_value(p, idx);
1257 track->db_s_write_offset = radeon_get_ib_value(p, idx);
1263 track->vgt_strmout_config = radeon_get_ib_value(p, idx);
1267 track->vgt_strmout_buffer_config = radeon_get_ib_value(p, idx);
1281 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1292 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
1305 track->cb_target_mask = radeon_get_ib_value(p, idx);
1309 track->cb_shader_mask = radeon_get_ib_value(p, idx);
1318 tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK;
1327 tmp = radeon_get_ib_value(p, idx) & CAYMAN_MSAA_NUM_SAMPLES_MASK;
1339 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
1347 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
1359 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1377 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1399 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
1407 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
1419 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
1428 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
1535 track->cb_color_fmask_slice[tmp] = radeon_get_ib_value(p, idx);
1546 track->cb_color_cmask_slice[tmp] = radeon_get_ib_value(p, idx);
1563 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
1579 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
1591 track->htile_offset = radeon_get_ib_value(p, idx);
1598 track->htile_surface = radeon_get_ib_value(p, idx);
1740 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;
1788 idx_value = radeon_get_ib_value(p, idx);
1802 tmp = radeon_get_ib_value(p, idx + 1);
1868 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
1903 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
1930 radeon_get_ib_value(p, idx+1) +
1931 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
2103 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
2104 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
2121 command = radeon_get_ib_value(p, idx+4);
2123 info = radeon_get_ib_value(p, idx+1);
2156 tmp = radeon_get_ib_value(p, idx) +
2157 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
2194 tmp = radeon_get_ib_value(p, idx+2) +
2195 ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32);
2226 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
2227 radeon_get_ib_value(p, idx + 2) != 0) {
2250 (radeon_get_ib_value(p, idx+1) & 0xfffffff8) +
2251 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
2272 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
2273 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
2294 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
2295 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
2353 switch (G__SQ_CONSTANT_TYPE(radeon_get_ib_value(p, idx+1+(i*8)+7))) {
2417 offset = radeon_get_ib_value(p, idx+1+(i*8)+0);
2418 size = radeon_get_ib_value(p, idx+1+(i*8)+1);
2499 offset = radeon_get_ib_value(p, idx+1);
2500 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2518 offset = radeon_get_ib_value(p, idx+3);
2519 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2543 offset = radeon_get_ib_value(p, idx+0);
2544 offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL;
2572 offset = radeon_get_ib_value(p, idx+1);
2573 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2584 reg = radeon_get_ib_value(p, idx+1) << 2;
2599 offset = radeon_get_ib_value(p, idx+3);
2600 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2611 reg = radeon_get_ib_value(p, idx+3) << 2;
2649 offset = radeon_get_ib_value(p, idx + 1);
2653 offset += ((u64)(radeon_get_ib_value(p, idx + 2) & 0xff)) << 32;
2677 offset = radeon_get_ib_value(p, idx + 0);
2678 offset += ((u64)(radeon_get_ib_value(p, idx + 1) & 0xff)) << 32UL;
2706 offset = radeon_get_ib_value(p, idx + 1);
2707 offset += ((u64)(radeon_get_ib_value(p, idx + 2) & 0xff)) << 32;
2718 reg = radeon_get_ib_value(p, idx + 1) << 2;
2733 offset = radeon_get_ib_value(p, idx + 5);
2734 offset += ((u64)(radeon_get_ib_value(p, idx + 6) & 0xff)) << 32;
2745 reg = radeon_get_ib_value(p, idx + 5) << 2;
2904 header = radeon_get_ib_value(p, idx);
2919 dst_offset = radeon_get_ib_value(p, idx+1);
2927 dst_offset = radeon_get_ib_value(p, idx+1);
2928 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2959 src_offset = radeon_get_ib_value(p, idx+2);
2960 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2961 dst_offset = radeon_get_ib_value(p, idx+1);
2962 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;
2982 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) {
2984 src_offset = radeon_get_ib_value(p, idx+1);
2988 dst_offset = radeon_get_ib_value(p, idx + 7);
2989 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;
2994 src_offset = radeon_get_ib_value(p, idx+7);
2995 src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;
2999 dst_offset = radeon_get_ib_value(p, idx+1);
3018 src_offset = radeon_get_ib_value(p, idx+2);
3019 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
3020 dst_offset = radeon_get_ib_value(p, idx+1);
3021 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;
3060 dst_offset = radeon_get_ib_value(p, idx+1);
3061 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
3062 dst2_offset = radeon_get_ib_value(p, idx+2);
3063 dst2_offset |= ((u64)(radeon_get_ib_value(p, idx+5) & 0xff)) << 32;
3064 src_offset = radeon_get_ib_value(p, idx+3);
3065 src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;
3091 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) {
3100 dst_offset = radeon_get_ib_value(p, idx+1);
3102 dst2_offset = radeon_get_ib_value(p, idx+2);
3104 src_offset = radeon_get_ib_value(p, idx+8);
3105 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;
3135 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) {
3153 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) {
3162 dst_offset = radeon_get_ib_value(p, idx+1);
3164 dst2_offset = radeon_get_ib_value(p, idx+2);
3166 src_offset = radeon_get_ib_value(p, idx+8);
3167 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;
3193 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) {
3195 src_offset = radeon_get_ib_value(p, idx+1);
3199 dst_offset = radeon_get_ib_value(p, idx+7);
3200 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;
3205 src_offset = radeon_get_ib_value(p, idx+7);
3206 src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;
3210 dst_offset = radeon_get_ib_value(p, idx+1);
3240 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) {
3249 dst_offset = radeon_get_ib_value(p, idx+1);
3251 dst2_offset = radeon_get_ib_value(p, idx+2);
3253 src_offset = radeon_get_ib_value(p, idx+8);
3254 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;
3287 dst_offset = radeon_get_ib_value(p, idx+1);
3288 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16;