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Searched refs:qm_err (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/crypto/hisilicon/sec2/
H A Dsec_main.c1207 struct hisi_qm_err_mask *qm_err = &err_info->qm_err; in sec_err_info_init() local
1210 qm_err->fe = SEC_RAS_FE_ENB_MSK; in sec_err_info_init()
1211 qm_err->ce = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_QM_CE_MASK_CAP, qm->cap_ver); in sec_err_info_init()
1212 qm_err->nfe = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_QM_NFE_MASK_CAP, qm->cap_ver); in sec_err_info_init()
1213 qm_err->shutdown_mask = hisi_qm_get_hw_info(qm, sec_basic_info, in sec_err_info_init()
1215 qm_err->reset_mask = hisi_qm_get_hw_info(qm, sec_basic_info, in sec_err_info_init()
1217 qm_err->ecc_2bits_mask = QM_ECC_MBIT; in sec_err_info_init()
/linux/drivers/crypto/hisilicon/zip/
H A Dzip_main.c1307 struct hisi_qm_err_mask *qm_err = &err_info->qm_err; in hisi_zip_err_info_init() local
1310 qm_err->fe = HZIP_CORE_INT_RAS_FE_ENB_MASK; in hisi_zip_err_info_init()
1311 qm_err->ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_QM_CE_MASK_CAP, qm->cap_ver); in hisi_zip_err_info_init()
1312 qm_err->nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, in hisi_zip_err_info_init()
1314 qm_err->ecc_2bits_mask = QM_ECC_MBIT; in hisi_zip_err_info_init()
1315 qm_err->reset_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, in hisi_zip_err_info_init()
1317 qm_err->shutdown_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, in hisi_zip_err_info_init()
/linux/drivers/crypto/hisilicon/hpre/
H A Dhpre_main.c1487 struct hisi_qm_err_mask *qm_err = &err_info->qm_err; in hpre_err_info_init() local
1490 qm_err->fe = HPRE_HAC_RAS_FE_ENABLE; in hpre_err_info_init()
1491 qm_err->ce = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_QM_CE_MASK_CAP, qm->cap_ver); in hpre_err_info_init()
1492 qm_err->nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_QM_NFE_MASK_CAP, qm->cap_ver); in hpre_err_info_init()
1493 qm_err->shutdown_mask = hisi_qm_get_hw_info(qm, hpre_basic_info, in hpre_err_info_init()
1495 qm_err->reset_mask = hisi_qm_get_hw_info(qm, hpre_basic_info, in hpre_err_info_init()
1497 qm_err->ecc_2bits_mask = QM_ECC_MBIT; in hpre_err_info_init()
/linux/drivers/crypto/hisilicon/
H A Dqm.c527 if (err_status & pf_qm->err_info.qm_err.shutdown_mask) in qm_check_dev_error()
1474 struct hisi_qm_err_mask *qm_err = &qm->err_info.qm_err; in qm_hw_error_cfg() local
1476 qm->error_mask = qm_err->nfe | qm_err->ce | qm_err->fe; in qm_hw_error_cfg()
1481 writel(qm_err->ce, qm->io_base + QM_RAS_CE_ENABLE); in qm_hw_error_cfg()
1483 writel(qm_err->nfe, qm->io_base + QM_RAS_NFE_ENABLE); in qm_hw_error_cfg()
1484 writel(qm_err->fe, qm->io_base + QM_RAS_FE_ENABLE); in qm_hw_error_cfg()
1513 writel(qm->err_info.qm_err.shutdown_mask, qm->io_base + QM_OOO_SHUTDOWN_SEL); in qm_hw_error_init_v3()
1575 struct hisi_qm_err_mask *qm_err = &qm->err_info.qm_err; in qm_hw_error_handle_v2() local
1584 if (error_status & qm_err->reset_mask) { in qm_hw_error_handle_v2()
1586 writel(qm_err->nfe & (~error_status), qm->io_base + QM_RAS_NFE_ENABLE); in qm_hw_error_handle_v2()
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/linux/include/linux/
H A Dhisi_acc_qm.h260 struct hisi_qm_err_mask qm_err; member