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Searched refs:dpll (Results 1 – 25 of 82) sorted by relevance

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/linux/drivers/dpll/
H A Ddpll_netlink.c34 dpll_msg_add_dev_handle(struct sk_buff *msg, struct dpll_device *dpll) in dpll_msg_add_dev_handle() argument
36 if (nla_put_u32(msg, DPLL_A_ID, dpll->id)) in dpll_msg_add_dev_handle()
63 if (xa_get_mark(&dpll_device_xa, par_ref->dpll->id, in dpll_pin_available()
110 dpll_msg_add_mode(struct sk_buff *msg, struct dpll_device *dpll, in dpll_msg_add_mode() argument
113 const struct dpll_device_ops *ops = dpll_device_ops(dpll); in dpll_msg_add_mode()
117 ret = ops->mode_get(dpll, dpll_priv(dpll), &mode, extack); in dpll_msg_add_mode()
127 dpll_msg_add_mode_supported(struct sk_buff *msg, struct dpll_device *dpll, in dpll_msg_add_mode_supported() argument
130 const struct dpll_device_ops *ops = dpll_device_ops(dpll); in dpll_msg_add_mode_supported()
136 ret = ops->supported_modes_get(dpll, dpll_priv(dpll), modes, in dpll_msg_add_mode_supported()
144 ret = ops->mode_get(dpll, dpll_priv(dpll), &mode, extack); in dpll_msg_add_mode_supported()
[all …]
H A Ddpll_core.c61 void dpll_device_notify(struct dpll_device *dpll, unsigned long action) in dpll_device_notify() argument
64 .dpll = dpll, in dpll_device_notify()
65 .id = dpll->id, in dpll_device_notify()
66 .idx = dpll->device_idx, in dpll_device_notify()
67 .clock_id = dpll->clock_id, in dpll_device_notify()
68 .type = dpll->type, in dpll_device_notify()
88 static void dpll_device_tracker_alloc(struct dpll_device *dpll, in dpll_device_tracker_alloc() argument
92 ref_tracker_alloc(&dpll->refcnt_tracker, tracker, GFP_KERNEL); in dpll_device_tracker_alloc()
96 static void dpll_device_tracker_free(struct dpll_device *dpll, in dpll_device_tracker_free() argument
100 ref_tracker_free(&dpll->refcnt_tracker, tracker); in dpll_device_tracker_free()
[all …]
H A DMakefile6 obj-$(CONFIG_DPLL) += dpll.o
7 dpll-y += dpll_core.o
8 dpll-y += dpll_netlink.o
9 dpll-y += dpll_nl.o
H A Ddpll_core.h81 struct dpll_device *dpll; member
88 void *dpll_priv(struct dpll_device *dpll);
89 void *dpll_pin_on_dpll_priv(struct dpll_device *dpll, struct dpll_pin *pin);
92 const struct dpll_device_ops *dpll_device_ops(struct dpll_device *dpll);
100 void dpll_device_notify(struct dpll_device *dpll, unsigned long action);
H A Ddpll_netlink.h7 int dpll_device_create_ntf(struct dpll_device *dpll);
9 int dpll_device_delete_ntf(struct dpll_device *dpll);
/linux/include/linux/
H A Ddpll.h24 int (*mode_get)(const struct dpll_device *dpll, void *dpll_priv,
26 int (*mode_set)(const struct dpll_device *dpll, void *dpll_priv,
28 int (*supported_modes_get)(const struct dpll_device *dpll,
31 int (*lock_status_get)(const struct dpll_device *dpll, void *dpll_priv,
35 int (*temp_get)(const struct dpll_device *dpll, void *dpll_priv,
37 int (*clock_quality_level_get)(const struct dpll_device *dpll,
41 int (*phase_offset_monitor_set)(const struct dpll_device *dpll,
45 int (*phase_offset_monitor_get)(const struct dpll_device *dpll,
49 int (*phase_offset_avg_factor_set)(const struct dpll_device *dpll,
52 int (*phase_offset_avg_factor_get)(const struct dpll_device *dpll,
[all …]
/linux/drivers/gpu/drm/gma500/
H A Dpsb_intel_display.c108 u32 dpll = 0, fp = 0, dspcntr, pipeconf; in psb_intel_crtc_mode_set() local
159 dpll = DPLL_VGA_MODE_DIS; in psb_intel_crtc_mode_set()
161 dpll |= DPLLB_MODE_LVDS; in psb_intel_crtc_mode_set()
162 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
164 dpll |= DPLLB_MODE_DAC_SERIAL; in psb_intel_crtc_mode_set()
168 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
169 dpll |= in psb_intel_crtc_mode_set()
174 dpll |= (1 << (clock.p1 - 1)) << 16; in psb_intel_crtc_mode_set()
177 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in psb_intel_crtc_mode_set()
180 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in psb_intel_crtc_mode_set()
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H A Doaktrail_crtc.c246 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
248 REG_WRITE_WITH_AUX(map->dpll, temp, i); in oaktrail_crtc_dpms()
249 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
252 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
254 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
257 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
259 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
318 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
320 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
322 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
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H A Dcdv_intel_display.c585 u32 dpll = 0, dspcntr, pipeconf; in cdv_intel_crtc_mode_set() local
666 dpll = DPLL_VGA_MODE_DIS; in cdv_intel_crtc_mode_set()
677 dpll |= DPLL_SYNCLOCK_ENABLE; in cdv_intel_crtc_mode_set()
723 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); in cdv_intel_crtc_mode_set()
724 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
759 dpll |= DPLL_VCO_ENABLE; in cdv_intel_crtc_mode_set()
768 REG_WRITE(map->dpll, in cdv_intel_crtc_mode_set()
769 (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE); in cdv_intel_crtc_mode_set()
770 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
774 if (!(REG_READ(map->dpll) & DPLL_LOCK)) { in cdv_intel_crtc_mode_set()
[all …]
H A Dgma_display.c223 temp = REG_READ(map->dpll); in gma_crtc_dpms()
225 REG_WRITE(map->dpll, temp); in gma_crtc_dpms()
226 REG_READ(map->dpll); in gma_crtc_dpms()
229 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
230 REG_READ(map->dpll); in gma_crtc_dpms()
233 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
234 REG_READ(map->dpll); in gma_crtc_dpms()
311 temp = REG_READ(map->dpll); in gma_crtc_dpms()
313 REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE); in gma_crtc_dpms()
314 REG_READ(map->dpll); in gma_crtc_dpms()
[all …]
H A Doaktrail_hdmi.c286 u32 dspcntr, pipeconf, dpll, temp; in oaktrail_crtc_hdmi_mode_set() local
296 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
297 if ((dpll & DPLL_PWRDN) == 0) { in oaktrail_crtc_hdmi_mode_set()
298 REG_WRITE(DPLL_CTRL, dpll | (DPLL_PWRDN | DPLL_RESET)); in oaktrail_crtc_hdmi_mode_set()
312 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
313 dpll &= ~DPLL_PDIV_MASK; in oaktrail_crtc_hdmi_mode_set()
314 dpll &= ~(DPLL_PWRDN | DPLL_RESET); in oaktrail_crtc_hdmi_mode_set()
318 REG_WRITE(DPLL_CTRL, (dpll | (clock.np << DPLL_PDIV_SHIFT) | DPLL_ENSTAT | DPLL_DITHEN)); in oaktrail_crtc_hdmi_mode_set()
/linux/Documentation/devicetree/bindings/clock/ti/
H A Ddpll.txt16 "ti,omap3-dpll-clock",
17 "ti,omap3-dpll-core-clock",
18 "ti,omap3-dpll-per-clock",
19 "ti,omap3-dpll-per-j-type-clock",
20 "ti,omap4-dpll-clock",
21 "ti,omap4-dpll-x2-clock",
22 "ti,omap4-dpll-core-clock",
23 "ti,omap4-dpll-m4xen-clock",
24 "ti,omap4-dpll-j-type-clock",
25 "ti,omap5-mpu-dpll-clock",
[all …]
/linux/Documentation/driver-api/
H A Ddpll.rst4 The Linux kernel dpll subsystem
22 The main purpose of dpll subsystem is to provide general interface
32 Single dpll device object means single Digital PLL circuit and bunch of
38 Changing the configuration of dpll device is done with `do` request of
52 The number of pins per dpll vary, but usually multiple pins shall be
53 provided for a single dpll device.
68 In general, selected pin (the one which signal is driving the dpll
70 one pin shall be in ``DPLL_PIN_STATE_CONNECTED`` state for any dpll
74 on hardware capabilities and active dpll device work mode
77 for the states the user can request for a dpll device.
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Dintel_dpll.h12 struct dpll;
24 int i9xx_calc_dpll_params(int refclk, struct dpll *clock);
25 u32 i9xx_dpll_compute_fp(const struct dpll *dpll);
32 const struct dpll *dpll);
42 struct dpll *best_clock);
43 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
H A Dg4x_dp.h21 const struct dpll *vlv_get_dpll(struct intel_display *display);
28 static inline const struct dpll *vlv_get_dpll(struct intel_display *display) in vlv_get_dpll()
/linux/drivers/net/ethernet/intel/ice/
H A Dice_dpll.c202 const struct dpll_device *dpll, void *dpll_priv, in ice_dpll_frequency_set() argument
240 const struct dpll_device *dpll, void *dpll_priv, in ice_dpll_input_frequency_set() argument
243 return ice_dpll_frequency_set(pin, pin_priv, dpll, dpll_priv, frequency, in ice_dpll_input_frequency_set()
265 const struct dpll_device *dpll, void *dpll_priv, in ice_dpll_output_frequency_set() argument
268 return ice_dpll_frequency_set(pin, pin_priv, dpll, dpll_priv, frequency, in ice_dpll_output_frequency_set()
291 const struct dpll_device *dpll, void *dpll_priv, in ice_dpll_frequency_get() argument
324 const struct dpll_device *dpll, void *dpll_priv, in ice_dpll_input_frequency_get() argument
327 return ice_dpll_frequency_get(pin, pin_priv, dpll, dpll_priv, frequency, in ice_dpll_input_frequency_get()
349 const struct dpll_device *dpll, void *dpll_priv, in ice_dpll_output_frequency_get() argument
352 return ice_dpll_frequency_get(pin, pin_priv, dpll, dpll_priv, frequency, in ice_dpll_output_frequency_get()
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/linux/drivers/net/ethernet/mellanox/mlx5/core/
H A Ddpll.c11 struct dpll_device *dpll; member
146 mlx5_dpll_device_lock_status_get(const struct dpll_device *dpll, void *priv, in mlx5_dpll_device_lock_status_get() argument
163 static int mlx5_dpll_device_mode_get(const struct dpll_device *dpll, in mlx5_dpll_device_mode_get() argument
200 static int mlx5_dpll_clock_quality_level_get(const struct dpll_device *dpll, in mlx5_dpll_clock_quality_level_get() argument
259 const struct dpll_device *dpll, in mlx5_dpll_pin_direction_get() argument
270 const struct dpll_device *dpll, in mlx5_dpll_state_on_dpll_get() argument
288 const struct dpll_device *dpll, in mlx5_dpll_state_on_dpll_set() argument
302 const struct dpll_device *dpll, void *dpll_priv, in mlx5_dpll_ffo_get() argument
354 dpll_device_change_ntf(mdpll->dpll); in mlx5_dpll_periodic_work()
443 mdpll->dpll = dpll_device_get(clock_id, 0, THIS_MODULE, in mlx5_dpll_probe()
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/linux/drivers/dpll/zl3073x/
H A Ddpll.c46 struct zl3073x_dpll *dpll; member
94 const struct dpll_device *dpll, void *dpll_priv, in zl3073x_dpll_pin_direction_get() argument
122 const struct dpll_device *dpll, in zl3073x_dpll_input_pin_esync_get() argument
164 const struct dpll_device *dpll, in zl3073x_dpll_input_pin_esync_set() argument
197 const struct dpll_device *dpll, void *dpll_priv, in zl3073x_dpll_input_pin_ffo_get() argument
210 const struct dpll_device *dpll, in zl3073x_dpll_input_pin_frequency_get() argument
227 const struct dpll_device *dpll, in zl3073x_dpll_input_pin_frequency_set() argument
403 const struct dpll_device *dpll, in zl3073x_dpll_input_pin_phase_offset_get() argument
462 const struct dpll_device *dpll, in zl3073x_dpll_input_pin_phase_adjust_get() argument
495 const struct dpll_device *dpll, in zl3073x_dpll_input_pin_phase_adjust_set() argument
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Ddra7xx-clocks.dtsi229 compatible = "ti,omap4-dpll-m4xen-clock";
235 dpll_abe_x2_ck: clock-dpll-abe-x2 {
237 compatible = "ti,omap4-dpll-x2-clock";
242 dpll_abe_m2x2_ck: clock-dpll-abe-m2x2-8@1f0 {
264 dpll_abe_m2_ck: clock-dpll-abe-m2-8@1f0 {
276 dpll_abe_m3x2_ck: clock-dpll-abe-m3x2-8@1f4 {
307 compatible = "ti,omap4-dpll-core-clock";
313 dpll_core_x2_ck: clock-dpll-core-x2 {
315 compatible = "ti,omap4-dpll-x2-clock";
320 dpll_core_h12x2_ck: clock-dpll-core-h12x2-8@13c {
[all …]
H A Dam43xx-clocks.dtsi231 compatible = "ti,am3-dpll-core-clock";
237 dpll_core_x2_ck: clock-dpll-core-x2 {
239 compatible = "ti,am3-dpll-x2-clock";
244 dpll_core_m4_ck: clock-dpll-core-m4-8@2d38 {
256 dpll_core_m5_ck: clock-dpll-core-m5-8@2d3c {
268 dpll_core_m6_ck: clock-dpll-core-m6-8@2d40 {
282 compatible = "ti,am3-dpll-clock";
288 dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@2d70 {
311 compatible = "ti,am3-dpll-clock";
317 dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@2db0 {
[all …]
H A Dam33xx-clocks.dtsi191 compatible = "ti,am3-dpll-core-clock";
197 dpll_core_x2_ck: clock-dpll-core-x2 {
199 compatible = "ti,am3-dpll-x2-clock";
204 dpll_core_m4_ck: clock-dpll-core-m4@480 {
214 dpll_core_m5_ck: clock-dpll-core-m5@484 {
224 dpll_core_m6_ck: clock-dpll-core-m6@4d8 {
236 compatible = "ti,am3-dpll-clock";
242 dpll_mpu_m2_ck: clock-dpll-mpu-m2@4a8 {
254 compatible = "ti,am3-dpll-no-gate-clock";
260 dpll_ddr_m2_ck: clock-dpll-ddr-m2@4a0 {
[all …]
/linux/arch/arm/mach-omap1/
H A Dsram.S36 strh r0, [r2] @ set dpll into bypass mode
41 strh r0, [r2] @ write new dpll value
49 lock: ldrh r4, [r2], #0 @ read back dpll value
52 tst r4, #1 << 0 @ dpll rate locked?
/linux/drivers/ata/
H A Dpata_hpt3x2n.c312 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_defer() local
319 if ((flags & USE_DPLL) != dpll && alt->qc_active) in hpt3x2n_qc_defer()
328 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_issue() local
330 if ((flags & USE_DPLL) != dpll) { in hpt3x2n_qc_issue()
332 flags |= dpll; in hpt3x2n_qc_issue()
335 hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23); in hpt3x2n_qc_issue()
/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_du_crtc.c84 struct dpll_info *dpll, in rcar_du_dpll_divider() argument
148 dpll->n = n; in rcar_du_dpll_divider()
149 dpll->m = m; in rcar_du_dpll_divider()
150 dpll->fdpll = fdpll; in rcar_du_dpll_divider()
151 dpll->output = output; in rcar_du_dpll_divider()
163 dpll->output, dpll->fdpll, dpll->n, dpll->m, best_diff); in rcar_du_dpll_divider()
218 struct dpll_info dpll = { 0 }; in rcar_du_crtc_set_display_timing() local
228 rcar_du_dpll_divider(rcrtc, &dpll, extclk, target); in rcar_du_crtc_set_display_timing()
231 | DPLLCR_FDPLL(dpll.fdpll) in rcar_du_crtc_set_display_timing()
232 | DPLLCR_N(dpll.n) | DPLLCR_M(dpll.m) in rcar_du_crtc_set_display_timing()
/linux/arch/arm64/boot/dts/sprd/
H A Dsharkl3.dtsi123 dpll: dpll@0 { label
124 compatible = "sprd,sc9863a-dpll";

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