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Searched refs:DISPCLK_FREQ_CHANGE_CNTL (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn303/
H A Ddcn303_dccg.h37 SR(DISPCLK_FREQ_CHANGE_CNTL),\
51 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_DELAY, mask_sh),\
52 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_SIZE, mask_sh),\
53 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_FREQ_RAMP_DONE, mask_sh),\
54 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_MAX_ERRDET_CYCLES, mask_sh),\
55 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_RESET, mask_sh),\
56 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_STATE, mask_sh),\
57 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_OVR_EN, mask_sh),\
58 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_CHG_FWD_CORR_DISABLE, mask_sh),\
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/
H A Ddcn20_dccg.h40 SR(DISPCLK_FREQ_CHANGE_CNTL),\
78 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_DELAY, mask_sh),\
79 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_SIZE, mask_sh),\
80 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_FREQ_RAMP_DONE, mask_sh),\
81 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_MAX_ERRDET_CYCLES, mask_sh),\
82 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_RESET, mask_sh),\
83 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_STATE, mask_sh),\
84 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_OVR_EN, mask_sh),\
85 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_CHG_FWD_CORR_DISABLE, mask_sh),\
137 type DISPCLK_FREQ_CHANGE_CNTL;\
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H A Ddcn20_dccg.c104 REG_UPDATE(DISPCLK_FREQ_CHANGE_CNTL, in dccg2_set_fifo_errdet_ovr_en()
142 REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x0e01003c); in dccg2_init()
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn35/
H A Ddcn35_dccg.h235 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_DELAY, mask_sh),\
236 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_SIZE, mask_sh),\
237 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_FREQ_RAMP_DONE, mask_sh),\
238 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_MAX_ERRDET_CYCLES, mask_sh),\
239 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_RESET, mask_sh),\
240 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_STATE, mask_sh),\
241 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_OVR_EN, mask_sh),\
242 DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_CHG_FWD_CORR_DISABLE, mask_sh),\
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn301/
H A Ddcn301_dccg.h38 SR(DISPCLK_FREQ_CHANGE_CNTL),\
/linux/drivers/gpu/drm/amd/display/dc/hwss/dce/
H A Ddce_hwseq.h266 SR(DISPCLK_FREQ_CHANGE_CNTL), \
330 SR(DISPCLK_FREQ_CHANGE_CNTL), \
377 SR(DISPCLK_FREQ_CHANGE_CNTL), \
401 SR(DISPCLK_FREQ_CHANGE_CNTL), \
438 SR(DISPCLK_FREQ_CHANGE_CNTL), \
490 SR(DISPCLK_FREQ_CHANGE_CNTL), \
550 SR(DISPCLK_FREQ_CHANGE_CNTL), \
640 uint32_t DISPCLK_FREQ_CHANGE_CNTL; member
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn36/
H A Ddcn36_resource.h45 SR(DISPCLK_FREQ_CHANGE_CNTL), \
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.h184 SR(DISPCLK_FREQ_CHANGE_CNTL), \
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn31/
H A Ddcn31_dccg.c756 dccg_reg_state->dispclk_freq_change_cntl = REG_READ(DISPCLK_FREQ_CHANGE_CNTL); in dccg31_read_reg_state()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/
H A Ddcn314_resource.c707 SR(DISPCLK_FREQ_CHANGE_CNTL), \
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/
H A Ddcn316_resource.c694 SR(DISPCLK_FREQ_CHANGE_CNTL), \
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn315/
H A Ddcn315_resource.c699 SR(DISPCLK_FREQ_CHANGE_CNTL), \
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/
H A Ddcn31_resource.c700 SR(DISPCLK_FREQ_CHANGE_CNTL), \
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/
H A Ddcn321_resource.c547 SR(DISPCLK_FREQ_CHANGE_CNTL), \
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/
H A Ddcn401_resource.c526 SR(DISPCLK_FREQ_CHANGE_CNTL), \
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.c551 SR(DISPCLK_FREQ_CHANGE_CNTL), \