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Searched hist:f669c99241adfcd4186aebff6990cefdac25125b (Results 1 – 16 of 16) sorted by relevance

/qemu/target/hexagon/
H A Dcpu.cf669c99241adfcd4186aebff6990cefdac25125b Wed Sep 13 22:06:21 UTC 2023 Richard Henderson <richard.henderson@linaro.org> target/*: Add instance_align to all cpu base classes

The omission of alignment has technically been wrong since
269bd5d8f61, where QEMU_ALIGNED was added to CPUTLBDescFast.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
/qemu/target/alpha/
H A Dcpu.cf669c99241adfcd4186aebff6990cefdac25125b Wed Sep 13 22:06:21 UTC 2023 Richard Henderson <richard.henderson@linaro.org> target/*: Add instance_align to all cpu base classes

The omission of alignment has technically been wrong since
269bd5d8f61, where QEMU_ALIGNED was added to CPUTLBDescFast.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
/qemu/target/rx/
H A Dcpu.cf669c99241adfcd4186aebff6990cefdac25125b Wed Sep 13 22:06:21 UTC 2023 Richard Henderson <richard.henderson@linaro.org> target/*: Add instance_align to all cpu base classes

The omission of alignment has technically been wrong since
269bd5d8f61, where QEMU_ALIGNED was added to CPUTLBDescFast.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
/qemu/target/avr/
H A Dcpu.cf669c99241adfcd4186aebff6990cefdac25125b Wed Sep 13 22:06:21 UTC 2023 Richard Henderson <richard.henderson@linaro.org> target/*: Add instance_align to all cpu base classes

The omission of alignment has technically been wrong since
269bd5d8f61, where QEMU_ALIGNED was added to CPUTLBDescFast.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
/qemu/target/tricore/
H A Dcpu.cf669c99241adfcd4186aebff6990cefdac25125b Wed Sep 13 22:06:21 UTC 2023 Richard Henderson <richard.henderson@linaro.org> target/*: Add instance_align to all cpu base classes

The omission of alignment has technically been wrong since
269bd5d8f61, where QEMU_ALIGNED was added to CPUTLBDescFast.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
/qemu/target/sh4/
H A Dcpu.cf669c99241adfcd4186aebff6990cefdac25125b Wed Sep 13 22:06:21 UTC 2023 Richard Henderson <richard.henderson@linaro.org> target/*: Add instance_align to all cpu base classes

The omission of alignment has technically been wrong since
269bd5d8f61, where QEMU_ALIGNED was added to CPUTLBDescFast.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
/qemu/target/openrisc/
H A Dcpu.cf669c99241adfcd4186aebff6990cefdac25125b Wed Sep 13 22:06:21 UTC 2023 Richard Henderson <richard.henderson@linaro.org> target/*: Add instance_align to all cpu base classes

The omission of alignment has technically been wrong since
269bd5d8f61, where QEMU_ALIGNED was added to CPUTLBDescFast.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
/qemu/target/xtensa/
H A Dcpu.cf669c99241adfcd4186aebff6990cefdac25125b Wed Sep 13 22:06:21 UTC 2023 Richard Henderson <richard.henderson@linaro.org> target/*: Add instance_align to all cpu base classes

The omission of alignment has technically been wrong since
269bd5d8f61, where QEMU_ALIGNED was added to CPUTLBDescFast.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
/qemu/target/hppa/
H A Dcpu.cf669c99241adfcd4186aebff6990cefdac25125b Wed Sep 13 22:06:21 UTC 2023 Richard Henderson <richard.henderson@linaro.org> target/*: Add instance_align to all cpu base classes

The omission of alignment has technically been wrong since
269bd5d8f61, where QEMU_ALIGNED was added to CPUTLBDescFast.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
/qemu/target/m68k/
H A Dcpu.cf669c99241adfcd4186aebff6990cefdac25125b Wed Sep 13 22:06:21 UTC 2023 Richard Henderson <richard.henderson@linaro.org> target/*: Add instance_align to all cpu base classes

The omission of alignment has technically been wrong since
269bd5d8f61, where QEMU_ALIGNED was added to CPUTLBDescFast.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
/qemu/target/microblaze/
H A Dcpu.cf669c99241adfcd4186aebff6990cefdac25125b Wed Sep 13 22:06:21 UTC 2023 Richard Henderson <richard.henderson@linaro.org> target/*: Add instance_align to all cpu base classes

The omission of alignment has technically been wrong since
269bd5d8f61, where QEMU_ALIGNED was added to CPUTLBDescFast.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
/qemu/target/loongarch/
H A Dcpu.cf669c99241adfcd4186aebff6990cefdac25125b Wed Sep 13 22:06:21 UTC 2023 Richard Henderson <richard.henderson@linaro.org> target/*: Add instance_align to all cpu base classes

The omission of alignment has technically been wrong since
269bd5d8f61, where QEMU_ALIGNED was added to CPUTLBDescFast.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
/qemu/target/sparc/
H A Dcpu.cf669c99241adfcd4186aebff6990cefdac25125b Wed Sep 13 22:06:21 UTC 2023 Richard Henderson <richard.henderson@linaro.org> target/*: Add instance_align to all cpu base classes

The omission of alignment has technically been wrong since
269bd5d8f61, where QEMU_ALIGNED was added to CPUTLBDescFast.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
/qemu/target/mips/
H A Dcpu.cf669c99241adfcd4186aebff6990cefdac25125b Wed Sep 13 22:06:21 UTC 2023 Richard Henderson <richard.henderson@linaro.org> target/*: Add instance_align to all cpu base classes

The omission of alignment has technically been wrong since
269bd5d8f61, where QEMU_ALIGNED was added to CPUTLBDescFast.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
/qemu/target/riscv/
H A Dcpu.cf669c99241adfcd4186aebff6990cefdac25125b Wed Sep 13 22:06:21 UTC 2023 Richard Henderson <richard.henderson@linaro.org> target/*: Add instance_align to all cpu base classes

The omission of alignment has technically been wrong since
269bd5d8f61, where QEMU_ALIGNED was added to CPUTLBDescFast.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
/qemu/target/i386/
H A Dcpu.cf669c99241adfcd4186aebff6990cefdac25125b Wed Sep 13 22:06:21 UTC 2023 Richard Henderson <richard.henderson@linaro.org> target/*: Add instance_align to all cpu base classes

The omission of alignment has technically been wrong since
269bd5d8f61, where QEMU_ALIGNED was added to CPUTLBDescFast.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>