1 /*
2 * TriCore emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
22 #include "cpu.h"
23 #include "exec/translation-block.h"
24 #include "qemu/error-report.h"
25 #include "tcg/debug-assert.h"
26 #include "accel/tcg/cpu-ops.h"
27
set_feature(CPUTriCoreState * env,int feature)28 static inline void set_feature(CPUTriCoreState *env, int feature)
29 {
30 env->features |= 1ULL << feature;
31 }
32
tricore_gdb_arch_name(CPUState * cs)33 static const gchar *tricore_gdb_arch_name(CPUState *cs)
34 {
35 return "tricore";
36 }
37
tricore_cpu_set_pc(CPUState * cs,vaddr value)38 static void tricore_cpu_set_pc(CPUState *cs, vaddr value)
39 {
40 cpu_env(cs)->PC = value & ~(target_ulong)1;
41 }
42
tricore_cpu_get_pc(CPUState * cs)43 static vaddr tricore_cpu_get_pc(CPUState *cs)
44 {
45 return cpu_env(cs)->PC;
46 }
47
tricore_get_tb_cpu_state(CPUState * cs)48 static TCGTBCPUState tricore_get_tb_cpu_state(CPUState *cs)
49 {
50 CPUTriCoreState *env = cpu_env(cs);
51
52 return (TCGTBCPUState){
53 .pc = env->PC,
54 .flags = FIELD_DP32(0, TB_FLAGS, PRIV, extract32(env->PSW, 10, 2)),
55 };
56 }
57
tricore_cpu_synchronize_from_tb(CPUState * cs,const TranslationBlock * tb)58 static void tricore_cpu_synchronize_from_tb(CPUState *cs,
59 const TranslationBlock *tb)
60 {
61 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
62 cpu_env(cs)->PC = tb->pc;
63 }
64
tricore_restore_state_to_opc(CPUState * cs,const TranslationBlock * tb,const uint64_t * data)65 static void tricore_restore_state_to_opc(CPUState *cs,
66 const TranslationBlock *tb,
67 const uint64_t *data)
68 {
69 cpu_env(cs)->PC = data[0];
70 }
71
tricore_cpu_reset_hold(Object * obj,ResetType type)72 static void tricore_cpu_reset_hold(Object *obj, ResetType type)
73 {
74 CPUState *cs = CPU(obj);
75 TriCoreCPUClass *tcc = TRICORE_CPU_GET_CLASS(obj);
76
77 if (tcc->parent_phases.hold) {
78 tcc->parent_phases.hold(obj, type);
79 }
80
81 cpu_state_reset(cpu_env(cs));
82 }
83
tricore_cpu_has_work(CPUState * cs)84 static bool tricore_cpu_has_work(CPUState *cs)
85 {
86 return true;
87 }
88
tricore_cpu_mmu_index(CPUState * cs,bool ifetch)89 static int tricore_cpu_mmu_index(CPUState *cs, bool ifetch)
90 {
91 return 0;
92 }
93
tricore_cpu_realizefn(DeviceState * dev,Error ** errp)94 static void tricore_cpu_realizefn(DeviceState *dev, Error **errp)
95 {
96 CPUState *cs = CPU(dev);
97 TriCoreCPU *cpu = TRICORE_CPU(dev);
98 TriCoreCPUClass *tcc = TRICORE_CPU_GET_CLASS(dev);
99 CPUTriCoreState *env = &cpu->env;
100 Error *local_err = NULL;
101
102 cpu_exec_realizefn(cs, &local_err);
103 if (local_err != NULL) {
104 error_propagate(errp, local_err);
105 return;
106 }
107
108 /* Some features automatically imply others */
109 if (tricore_has_feature(env, TRICORE_FEATURE_162)) {
110 set_feature(env, TRICORE_FEATURE_161);
111 }
112
113 if (tricore_has_feature(env, TRICORE_FEATURE_161)) {
114 set_feature(env, TRICORE_FEATURE_16);
115 }
116
117 if (tricore_has_feature(env, TRICORE_FEATURE_16)) {
118 set_feature(env, TRICORE_FEATURE_131);
119 }
120 if (tricore_has_feature(env, TRICORE_FEATURE_131)) {
121 set_feature(env, TRICORE_FEATURE_13);
122 }
123 cpu_reset(cs);
124 qemu_init_vcpu(cs);
125
126 tcc->parent_realize(dev, errp);
127 }
128
tricore_cpu_class_by_name(const char * cpu_model)129 static ObjectClass *tricore_cpu_class_by_name(const char *cpu_model)
130 {
131 ObjectClass *oc;
132 char *typename;
133
134 typename = g_strdup_printf(TRICORE_CPU_TYPE_NAME("%s"), cpu_model);
135 oc = object_class_by_name(typename);
136 g_free(typename);
137
138 return oc;
139 }
140
tc1796_initfn(Object * obj)141 static void tc1796_initfn(Object *obj)
142 {
143 TriCoreCPU *cpu = TRICORE_CPU(obj);
144
145 set_feature(&cpu->env, TRICORE_FEATURE_13);
146 }
147
tc1797_initfn(Object * obj)148 static void tc1797_initfn(Object *obj)
149 {
150 TriCoreCPU *cpu = TRICORE_CPU(obj);
151
152 set_feature(&cpu->env, TRICORE_FEATURE_131);
153 }
154
tc27x_initfn(Object * obj)155 static void tc27x_initfn(Object *obj)
156 {
157 TriCoreCPU *cpu = TRICORE_CPU(obj);
158
159 set_feature(&cpu->env, TRICORE_FEATURE_161);
160 }
161
tc37x_initfn(Object * obj)162 static void tc37x_initfn(Object *obj)
163 {
164 TriCoreCPU *cpu = TRICORE_CPU(obj);
165
166 set_feature(&cpu->env, TRICORE_FEATURE_162);
167 }
168
tricore_cpu_exec_interrupt(CPUState * cs,int interrupt_request)169 static bool tricore_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
170 {
171 /* Interrupts are not implemented */
172 return false;
173 }
174
175 #include "hw/core/sysemu-cpu-ops.h"
176
177 static const struct SysemuCPUOps tricore_sysemu_ops = {
178 .has_work = tricore_cpu_has_work,
179 .get_phys_page_debug = tricore_cpu_get_phys_page_debug,
180 };
181
182 static const TCGCPUOps tricore_tcg_ops = {
183 /* MTTCG not yet supported: require strict ordering */
184 .guest_default_memory_order = TCG_MO_ALL,
185 .mttcg_supported = false,
186 .initialize = tricore_tcg_init,
187 .translate_code = tricore_translate_code,
188 .get_tb_cpu_state = tricore_get_tb_cpu_state,
189 .synchronize_from_tb = tricore_cpu_synchronize_from_tb,
190 .restore_state_to_opc = tricore_restore_state_to_opc,
191 .mmu_index = tricore_cpu_mmu_index,
192 .tlb_fill = tricore_cpu_tlb_fill,
193 .cpu_exec_interrupt = tricore_cpu_exec_interrupt,
194 .cpu_exec_halt = tricore_cpu_has_work,
195 .cpu_exec_reset = cpu_reset,
196 };
197
tricore_cpu_class_init(ObjectClass * c,const void * data)198 static void tricore_cpu_class_init(ObjectClass *c, const void *data)
199 {
200 TriCoreCPUClass *mcc = TRICORE_CPU_CLASS(c);
201 CPUClass *cc = CPU_CLASS(c);
202 DeviceClass *dc = DEVICE_CLASS(c);
203 ResettableClass *rc = RESETTABLE_CLASS(c);
204
205 device_class_set_parent_realize(dc, tricore_cpu_realizefn,
206 &mcc->parent_realize);
207
208 resettable_class_set_parent_phases(rc, NULL, tricore_cpu_reset_hold, NULL,
209 &mcc->parent_phases);
210 cc->class_by_name = tricore_cpu_class_by_name;
211
212 cc->gdb_read_register = tricore_cpu_gdb_read_register;
213 cc->gdb_write_register = tricore_cpu_gdb_write_register;
214 cc->gdb_num_core_regs = 44;
215 cc->gdb_arch_name = tricore_gdb_arch_name;
216
217 cc->dump_state = tricore_cpu_dump_state;
218 cc->set_pc = tricore_cpu_set_pc;
219 cc->get_pc = tricore_cpu_get_pc;
220 cc->sysemu_ops = &tricore_sysemu_ops;
221 cc->tcg_ops = &tricore_tcg_ops;
222 }
223
224 #define DEFINE_TRICORE_CPU_TYPE(cpu_model, initfn) \
225 { \
226 .parent = TYPE_TRICORE_CPU, \
227 .instance_init = initfn, \
228 .name = TRICORE_CPU_TYPE_NAME(cpu_model), \
229 }
230
231 static const TypeInfo tricore_cpu_type_infos[] = {
232 {
233 .name = TYPE_TRICORE_CPU,
234 .parent = TYPE_CPU,
235 .instance_size = sizeof(TriCoreCPU),
236 .instance_align = __alignof(TriCoreCPU),
237 .abstract = true,
238 .class_size = sizeof(TriCoreCPUClass),
239 .class_init = tricore_cpu_class_init,
240 },
241 DEFINE_TRICORE_CPU_TYPE("tc1796", tc1796_initfn),
242 DEFINE_TRICORE_CPU_TYPE("tc1797", tc1797_initfn),
243 DEFINE_TRICORE_CPU_TYPE("tc27x", tc27x_initfn),
244 DEFINE_TRICORE_CPU_TYPE("tc37x", tc37x_initfn),
245 };
246
247 DEFINE_TYPES(tricore_cpu_type_infos)
248