1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * QEMU LoongArch CPU
4 *
5 * Copyright (c) 2021 Loongson Technology Corporation Limited
6 */
7
8 #include "qemu/osdep.h"
9 #include "qemu/log.h"
10 #include "qemu/qemu-print.h"
11 #include "qapi/error.h"
12 #include "qemu/module.h"
13 #include "system/qtest.h"
14 #include "system/tcg.h"
15 #include "system/kvm.h"
16 #include "kvm/kvm_loongarch.h"
17 #include "hw/qdev-properties.h"
18 #include "exec/translation-block.h"
19 #include "cpu.h"
20 #include "internals.h"
21 #include "fpu/softfloat-helpers.h"
22 #include "csr.h"
23 #ifndef CONFIG_USER_ONLY
24 #include "system/reset.h"
25 #endif
26 #include "vec.h"
27 #ifdef CONFIG_KVM
28 #include <linux/kvm.h>
29 #endif
30 #ifdef CONFIG_TCG
31 #include "accel/tcg/cpu-ldst.h"
32 #include "accel/tcg/cpu-ops.h"
33 #include "tcg/tcg.h"
34 #endif
35 #include "tcg/tcg_loongarch.h"
36
37 const char * const regnames[32] = {
38 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
39 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
40 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
41 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
42 };
43
44 const char * const fregnames[32] = {
45 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
46 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
47 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
48 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
49 };
50
51 struct TypeExcp {
52 int32_t exccode;
53 const char * const name;
54 };
55
56 static const struct TypeExcp excp_names[] = {
57 {EXCCODE_INT, "Interrupt"},
58 {EXCCODE_PIL, "Page invalid exception for load"},
59 {EXCCODE_PIS, "Page invalid exception for store"},
60 {EXCCODE_PIF, "Page invalid exception for fetch"},
61 {EXCCODE_PME, "Page modified exception"},
62 {EXCCODE_PNR, "Page Not Readable exception"},
63 {EXCCODE_PNX, "Page Not Executable exception"},
64 {EXCCODE_PPI, "Page Privilege error"},
65 {EXCCODE_ADEF, "Address error for instruction fetch"},
66 {EXCCODE_ADEM, "Address error for Memory access"},
67 {EXCCODE_SYS, "Syscall"},
68 {EXCCODE_BRK, "Break"},
69 {EXCCODE_INE, "Instruction Non-Existent"},
70 {EXCCODE_IPE, "Instruction privilege error"},
71 {EXCCODE_FPD, "Floating Point Disabled"},
72 {EXCCODE_FPE, "Floating Point Exception"},
73 {EXCCODE_DBP, "Debug breakpoint"},
74 {EXCCODE_BCE, "Bound Check Exception"},
75 {EXCCODE_SXD, "128 bit vector instructions Disable exception"},
76 {EXCCODE_ASXD, "256 bit vector instructions Disable exception"},
77 {EXCP_HLT, "EXCP_HLT"},
78 };
79
loongarch_exception_name(int32_t exception)80 const char *loongarch_exception_name(int32_t exception)
81 {
82 int i;
83
84 for (i = 0; i < ARRAY_SIZE(excp_names); i++) {
85 if (excp_names[i].exccode == exception) {
86 return excp_names[i].name;
87 }
88 }
89 return "Unknown";
90 }
91
do_raise_exception(CPULoongArchState * env,uint32_t exception,uintptr_t pc)92 void G_NORETURN do_raise_exception(CPULoongArchState *env,
93 uint32_t exception,
94 uintptr_t pc)
95 {
96 CPUState *cs = env_cpu(env);
97
98 qemu_log_mask(CPU_LOG_INT, "%s: exception: %d (%s)\n",
99 __func__,
100 exception,
101 loongarch_exception_name(exception));
102 cs->exception_index = exception;
103
104 cpu_loop_exit_restore(cs, pc);
105 }
106
loongarch_cpu_set_pc(CPUState * cs,vaddr value)107 static void loongarch_cpu_set_pc(CPUState *cs, vaddr value)
108 {
109 set_pc(cpu_env(cs), value);
110 }
111
loongarch_cpu_get_pc(CPUState * cs)112 static vaddr loongarch_cpu_get_pc(CPUState *cs)
113 {
114 return cpu_env(cs)->pc;
115 }
116
117 #ifndef CONFIG_USER_ONLY
118 #include "hw/loongarch/virt.h"
119
loongarch_cpu_set_irq(void * opaque,int irq,int level)120 void loongarch_cpu_set_irq(void *opaque, int irq, int level)
121 {
122 LoongArchCPU *cpu = opaque;
123 CPULoongArchState *env = &cpu->env;
124 CPUState *cs = CPU(cpu);
125
126 if (irq < 0 || irq >= N_IRQS) {
127 return;
128 }
129
130 if (kvm_enabled()) {
131 kvm_loongarch_set_interrupt(cpu, irq, level);
132 } else if (tcg_enabled()) {
133 env->CSR_ESTAT = deposit64(env->CSR_ESTAT, irq, 1, level != 0);
134 if (FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS)) {
135 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
136 } else {
137 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
138 }
139 }
140 }
141
cpu_loongarch_hw_interrupts_enabled(CPULoongArchState * env)142 static inline bool cpu_loongarch_hw_interrupts_enabled(CPULoongArchState *env)
143 {
144 bool ret = 0;
145
146 ret = (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE) &&
147 !(FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)));
148
149 return ret;
150 }
151
152 /* Check if there is pending and not masked out interrupt */
cpu_loongarch_hw_interrupts_pending(CPULoongArchState * env)153 static inline bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env)
154 {
155 uint32_t pending;
156 uint32_t status;
157
158 pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS);
159 status = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE);
160
161 return (pending & status) != 0;
162 }
163 #endif
164
165 #ifdef CONFIG_TCG
166 #ifndef CONFIG_USER_ONLY
loongarch_cpu_do_interrupt(CPUState * cs)167 static void loongarch_cpu_do_interrupt(CPUState *cs)
168 {
169 CPULoongArchState *env = cpu_env(cs);
170 bool update_badinstr = 1;
171 int cause = -1;
172 bool tlbfill = FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR);
173 uint32_t vec_size = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, VS);
174
175 if (cs->exception_index != EXCCODE_INT) {
176 qemu_log_mask(CPU_LOG_INT,
177 "%s enter: pc " TARGET_FMT_lx " ERA " TARGET_FMT_lx
178 " TLBRERA " TARGET_FMT_lx " exception: %d (%s)\n",
179 __func__, env->pc, env->CSR_ERA, env->CSR_TLBRERA,
180 cs->exception_index,
181 loongarch_exception_name(cs->exception_index));
182 }
183
184 switch (cs->exception_index) {
185 case EXCCODE_DBP:
186 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DCL, 1);
187 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, ECODE, 0xC);
188 goto set_DERA;
189 set_DERA:
190 env->CSR_DERA = env->pc;
191 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DST, 1);
192 set_pc(env, env->CSR_EENTRY + 0x480);
193 break;
194 case EXCCODE_INT:
195 if (FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) {
196 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DEI, 1);
197 goto set_DERA;
198 }
199 QEMU_FALLTHROUGH;
200 case EXCCODE_PIF:
201 case EXCCODE_ADEF:
202 cause = cs->exception_index;
203 update_badinstr = 0;
204 break;
205 case EXCCODE_SYS:
206 case EXCCODE_BRK:
207 case EXCCODE_INE:
208 case EXCCODE_IPE:
209 case EXCCODE_FPD:
210 case EXCCODE_FPE:
211 case EXCCODE_SXD:
212 case EXCCODE_ASXD:
213 env->CSR_BADV = env->pc;
214 QEMU_FALLTHROUGH;
215 case EXCCODE_BCE:
216 case EXCCODE_ADEM:
217 case EXCCODE_PIL:
218 case EXCCODE_PIS:
219 case EXCCODE_PME:
220 case EXCCODE_PNR:
221 case EXCCODE_PNX:
222 case EXCCODE_PPI:
223 cause = cs->exception_index;
224 break;
225 default:
226 qemu_log("Error: exception(%d) has not been supported\n",
227 cs->exception_index);
228 abort();
229 }
230
231 if (update_badinstr) {
232 env->CSR_BADI = cpu_ldl_code(env, env->pc);
233 }
234
235 /* Save PLV and IE */
236 if (tlbfill) {
237 env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PPLV,
238 FIELD_EX64(env->CSR_CRMD,
239 CSR_CRMD, PLV));
240 env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PIE,
241 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE));
242 /* set the DA mode */
243 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1);
244 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0);
245 env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA,
246 PC, (env->pc >> 2));
247 } else {
248 env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE,
249 EXCODE_MCODE(cause));
250 env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ESUBCODE,
251 EXCODE_SUBCODE(cause));
252 env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PPLV,
253 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV));
254 env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PIE,
255 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE));
256 env->CSR_ERA = env->pc;
257 }
258
259 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0);
260 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0);
261
262 if (vec_size) {
263 vec_size = (1 << vec_size) * 4;
264 }
265
266 if (cs->exception_index == EXCCODE_INT) {
267 /* Interrupt */
268 uint32_t vector = 0;
269 uint32_t pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS);
270 pending &= FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE);
271
272 /* Find the highest-priority interrupt. */
273 vector = 31 - clz32(pending);
274 set_pc(env, env->CSR_EENTRY + \
275 (EXCCODE_EXTERNAL_INT + vector) * vec_size);
276 qemu_log_mask(CPU_LOG_INT,
277 "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx
278 " cause %d\n" " A " TARGET_FMT_lx " D "
279 TARGET_FMT_lx " vector = %d ExC " TARGET_FMT_lx "ExS"
280 TARGET_FMT_lx "\n",
281 __func__, env->pc, env->CSR_ERA,
282 cause, env->CSR_BADV, env->CSR_DERA, vector,
283 env->CSR_ECFG, env->CSR_ESTAT);
284 } else {
285 if (tlbfill) {
286 set_pc(env, env->CSR_TLBRENTRY);
287 } else {
288 set_pc(env, env->CSR_EENTRY + EXCODE_MCODE(cause) * vec_size);
289 }
290 qemu_log_mask(CPU_LOG_INT,
291 "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx
292 " cause %d%s\n, ESTAT " TARGET_FMT_lx
293 " EXCFG " TARGET_FMT_lx " BADVA " TARGET_FMT_lx
294 "BADI " TARGET_FMT_lx " SYS_NUM " TARGET_FMT_lu
295 " cpu %d asid " TARGET_FMT_lx "\n", __func__, env->pc,
296 tlbfill ? env->CSR_TLBRERA : env->CSR_ERA,
297 cause, tlbfill ? "(refill)" : "", env->CSR_ESTAT,
298 env->CSR_ECFG,
299 tlbfill ? env->CSR_TLBRBADV : env->CSR_BADV,
300 env->CSR_BADI, env->gpr[11], cs->cpu_index,
301 env->CSR_ASID);
302 }
303 cs->exception_index = -1;
304 }
305
loongarch_cpu_do_transaction_failed(CPUState * cs,hwaddr physaddr,vaddr addr,unsigned size,MMUAccessType access_type,int mmu_idx,MemTxAttrs attrs,MemTxResult response,uintptr_t retaddr)306 static void loongarch_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
307 vaddr addr, unsigned size,
308 MMUAccessType access_type,
309 int mmu_idx, MemTxAttrs attrs,
310 MemTxResult response,
311 uintptr_t retaddr)
312 {
313 CPULoongArchState *env = cpu_env(cs);
314
315 if (access_type == MMU_INST_FETCH) {
316 do_raise_exception(env, EXCCODE_ADEF, retaddr);
317 } else {
318 do_raise_exception(env, EXCCODE_ADEM, retaddr);
319 }
320 }
321
loongarch_cpu_exec_interrupt(CPUState * cs,int interrupt_request)322 static bool loongarch_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
323 {
324 if (interrupt_request & CPU_INTERRUPT_HARD) {
325 CPULoongArchState *env = cpu_env(cs);
326
327 if (cpu_loongarch_hw_interrupts_enabled(env) &&
328 cpu_loongarch_hw_interrupts_pending(env)) {
329 /* Raise it */
330 cs->exception_index = EXCCODE_INT;
331 loongarch_cpu_do_interrupt(cs);
332 return true;
333 }
334 }
335 return false;
336 }
337 #endif
338
loongarch_get_tb_cpu_state(CPUState * cs)339 static TCGTBCPUState loongarch_get_tb_cpu_state(CPUState *cs)
340 {
341 CPULoongArchState *env = cpu_env(cs);
342 uint32_t flags;
343
344 flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK);
345 flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE;
346 flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SXE;
347 flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_ASXE;
348 flags |= is_va32(env) * HW_FLAGS_VA32;
349
350 return (TCGTBCPUState){ .pc = env->pc, .flags = flags };
351 }
352
loongarch_cpu_synchronize_from_tb(CPUState * cs,const TranslationBlock * tb)353 static void loongarch_cpu_synchronize_from_tb(CPUState *cs,
354 const TranslationBlock *tb)
355 {
356 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
357 set_pc(cpu_env(cs), tb->pc);
358 }
359
loongarch_restore_state_to_opc(CPUState * cs,const TranslationBlock * tb,const uint64_t * data)360 static void loongarch_restore_state_to_opc(CPUState *cs,
361 const TranslationBlock *tb,
362 const uint64_t *data)
363 {
364 set_pc(cpu_env(cs), data[0]);
365 }
366 #endif /* CONFIG_TCG */
367
368 #ifndef CONFIG_USER_ONLY
loongarch_cpu_has_work(CPUState * cs)369 static bool loongarch_cpu_has_work(CPUState *cs)
370 {
371 bool has_work = false;
372
373 if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
374 cpu_loongarch_hw_interrupts_pending(cpu_env(cs))) {
375 has_work = true;
376 }
377
378 return has_work;
379 }
380 #endif /* !CONFIG_USER_ONLY */
381
loongarch_cpu_mmu_index(CPUState * cs,bool ifetch)382 static int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch)
383 {
384 CPULoongArchState *env = cpu_env(cs);
385
386 if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) {
387 return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV);
388 }
389 return MMU_DA_IDX;
390 }
391
loongarch_la464_init_csr(Object * obj)392 static void loongarch_la464_init_csr(Object *obj)
393 {
394 #ifndef CONFIG_USER_ONLY
395 static bool initialized;
396 LoongArchCPU *cpu = LOONGARCH_CPU(obj);
397 CPULoongArchState *env = &cpu->env;
398 int i, num;
399
400 if (!initialized) {
401 initialized = true;
402 num = FIELD_EX64(env->CSR_PRCFG1, CSR_PRCFG1, SAVE_NUM);
403 for (i = num; i < 16; i++) {
404 set_csr_flag(LOONGARCH_CSR_SAVE(i), CSRFL_UNUSED);
405 }
406 set_csr_flag(LOONGARCH_CSR_IMPCTL1, CSRFL_UNUSED);
407 set_csr_flag(LOONGARCH_CSR_IMPCTL2, CSRFL_UNUSED);
408 set_csr_flag(LOONGARCH_CSR_MERRCTL, CSRFL_UNUSED);
409 set_csr_flag(LOONGARCH_CSR_MERRINFO1, CSRFL_UNUSED);
410 set_csr_flag(LOONGARCH_CSR_MERRINFO2, CSRFL_UNUSED);
411 set_csr_flag(LOONGARCH_CSR_MERRENTRY, CSRFL_UNUSED);
412 set_csr_flag(LOONGARCH_CSR_MERRERA, CSRFL_UNUSED);
413 set_csr_flag(LOONGARCH_CSR_MERRSAVE, CSRFL_UNUSED);
414 set_csr_flag(LOONGARCH_CSR_CTAG, CSRFL_UNUSED);
415 }
416 #endif
417 }
418
loongarch_la464_initfn(Object * obj)419 static void loongarch_la464_initfn(Object *obj)
420 {
421 LoongArchCPU *cpu = LOONGARCH_CPU(obj);
422 CPULoongArchState *env = &cpu->env;
423 uint32_t data = 0, field;
424 int i;
425
426 for (i = 0; i < 21; i++) {
427 env->cpucfg[i] = 0x0;
428 }
429
430 cpu->dtb_compatible = "loongarch,Loongson-3A5000";
431 env->cpucfg[0] = 0x14c010; /* PRID */
432
433 data = FIELD_DP32(data, CPUCFG1, ARCH, 2);
434 data = FIELD_DP32(data, CPUCFG1, PGMMU, 1);
435 data = FIELD_DP32(data, CPUCFG1, IOCSR, 1);
436 if (kvm_enabled()) {
437 /* GPA address width of VM is 47, field value is 47 - 1 */
438 field = 0x2e;
439 } else {
440 field = 0x2f; /* 48 bit - 1 */
441 }
442 data = FIELD_DP32(data, CPUCFG1, PALEN, field);
443 data = FIELD_DP32(data, CPUCFG1, VALEN, 0x2f);
444 data = FIELD_DP32(data, CPUCFG1, UAL, 1);
445 data = FIELD_DP32(data, CPUCFG1, RI, 1);
446 data = FIELD_DP32(data, CPUCFG1, EP, 1);
447 data = FIELD_DP32(data, CPUCFG1, RPLV, 1);
448 data = FIELD_DP32(data, CPUCFG1, HP, 1);
449 data = FIELD_DP32(data, CPUCFG1, CRC, 1);
450 env->cpucfg[1] = data;
451
452 data = 0;
453 data = FIELD_DP32(data, CPUCFG2, FP, 1);
454 data = FIELD_DP32(data, CPUCFG2, FP_SP, 1);
455 data = FIELD_DP32(data, CPUCFG2, FP_DP, 1);
456 data = FIELD_DP32(data, CPUCFG2, FP_VER, 1);
457 data = FIELD_DP32(data, CPUCFG2, LSX, 1),
458 data = FIELD_DP32(data, CPUCFG2, LASX, 1),
459 data = FIELD_DP32(data, CPUCFG2, LLFTP, 1);
460 data = FIELD_DP32(data, CPUCFG2, LLFTP_VER, 1);
461 data = FIELD_DP32(data, CPUCFG2, LSPW, 1);
462 data = FIELD_DP32(data, CPUCFG2, LAM, 1);
463 env->cpucfg[2] = data;
464
465 env->cpucfg[4] = 100 * 1000 * 1000; /* Crystal frequency */
466
467 data = 0;
468 data = FIELD_DP32(data, CPUCFG5, CC_MUL, 1);
469 data = FIELD_DP32(data, CPUCFG5, CC_DIV, 1);
470 env->cpucfg[5] = data;
471
472 data = 0;
473 data = FIELD_DP32(data, CPUCFG16, L1_IUPRE, 1);
474 data = FIELD_DP32(data, CPUCFG16, L1_DPRE, 1);
475 data = FIELD_DP32(data, CPUCFG16, L2_IUPRE, 1);
476 data = FIELD_DP32(data, CPUCFG16, L2_IUUNIFY, 1);
477 data = FIELD_DP32(data, CPUCFG16, L2_IUPRIV, 1);
478 data = FIELD_DP32(data, CPUCFG16, L3_IUPRE, 1);
479 data = FIELD_DP32(data, CPUCFG16, L3_IUUNIFY, 1);
480 data = FIELD_DP32(data, CPUCFG16, L3_IUINCL, 1);
481 env->cpucfg[16] = data;
482
483 data = 0;
484 data = FIELD_DP32(data, CPUCFG17, L1IU_WAYS, 3);
485 data = FIELD_DP32(data, CPUCFG17, L1IU_SETS, 8);
486 data = FIELD_DP32(data, CPUCFG17, L1IU_SIZE, 6);
487 env->cpucfg[17] = data;
488
489 data = 0;
490 data = FIELD_DP32(data, CPUCFG18, L1D_WAYS, 3);
491 data = FIELD_DP32(data, CPUCFG18, L1D_SETS, 8);
492 data = FIELD_DP32(data, CPUCFG18, L1D_SIZE, 6);
493 env->cpucfg[18] = data;
494
495 data = 0;
496 data = FIELD_DP32(data, CPUCFG19, L2IU_WAYS, 15);
497 data = FIELD_DP32(data, CPUCFG19, L2IU_SETS, 8);
498 data = FIELD_DP32(data, CPUCFG19, L2IU_SIZE, 6);
499 env->cpucfg[19] = data;
500
501 data = 0;
502 data = FIELD_DP32(data, CPUCFG20, L3IU_WAYS, 15);
503 data = FIELD_DP32(data, CPUCFG20, L3IU_SETS, 14);
504 data = FIELD_DP32(data, CPUCFG20, L3IU_SIZE, 6);
505 env->cpucfg[20] = data;
506
507 env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa);
508
509 env->CSR_PRCFG1 = FIELD_DP64(env->CSR_PRCFG1, CSR_PRCFG1, SAVE_NUM, 8);
510 env->CSR_PRCFG1 = FIELD_DP64(env->CSR_PRCFG1, CSR_PRCFG1, TIMER_BITS, 0x2f);
511 env->CSR_PRCFG1 = FIELD_DP64(env->CSR_PRCFG1, CSR_PRCFG1, VSMAX, 7);
512
513 env->CSR_PRCFG2 = 0x3ffff000;
514
515 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, TLB_TYPE, 2);
516 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, MTLB_ENTRY, 63);
517 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS, 7);
518 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS, 8);
519
520 loongarch_la464_init_csr(obj);
521 loongarch_cpu_post_init(obj);
522 }
523
loongarch_la132_initfn(Object * obj)524 static void loongarch_la132_initfn(Object *obj)
525 {
526 LoongArchCPU *cpu = LOONGARCH_CPU(obj);
527 CPULoongArchState *env = &cpu->env;
528 uint32_t data = 0;
529 int i;
530
531 for (i = 0; i < 21; i++) {
532 env->cpucfg[i] = 0x0;
533 }
534
535 cpu->dtb_compatible = "loongarch,Loongson-1C103";
536 env->cpucfg[0] = 0x148042; /* PRID */
537
538 data = FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */
539 data = FIELD_DP32(data, CPUCFG1, PGMMU, 1);
540 data = FIELD_DP32(data, CPUCFG1, IOCSR, 1);
541 data = FIELD_DP32(data, CPUCFG1, PALEN, 0x1f); /* 32 bits */
542 data = FIELD_DP32(data, CPUCFG1, VALEN, 0x1f); /* 32 bits */
543 data = FIELD_DP32(data, CPUCFG1, UAL, 1);
544 data = FIELD_DP32(data, CPUCFG1, RI, 0);
545 data = FIELD_DP32(data, CPUCFG1, EP, 0);
546 data = FIELD_DP32(data, CPUCFG1, RPLV, 0);
547 data = FIELD_DP32(data, CPUCFG1, HP, 1);
548 data = FIELD_DP32(data, CPUCFG1, CRC, 1);
549 env->cpucfg[1] = data;
550 }
551
loongarch_max_initfn(Object * obj)552 static void loongarch_max_initfn(Object *obj)
553 {
554 /* '-cpu max' for TCG: we use cpu la464. */
555 loongarch_la464_initfn(obj);
556 }
557
loongarch_cpu_reset_hold(Object * obj,ResetType type)558 static void loongarch_cpu_reset_hold(Object *obj, ResetType type)
559 {
560 uint8_t tlb_ps;
561 CPUState *cs = CPU(obj);
562 LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(obj);
563 CPULoongArchState *env = cpu_env(cs);
564
565 if (lacc->parent_phases.hold) {
566 lacc->parent_phases.hold(obj, type);
567 }
568
569 #ifdef CONFIG_TCG
570 env->fcsr0_mask = FCSR0_M1 | FCSR0_M2 | FCSR0_M3;
571 #endif
572 env->fcsr0 = 0x0;
573
574 int n;
575 /* Set csr registers value after reset, see the manual 6.4. */
576 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0);
577 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0);
578 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1);
579 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0);
580 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATF, 0);
581 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATM, 0);
582
583 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, FPE, 0);
584 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, SXE, 0);
585 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, ASXE, 0);
586 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, BTE, 0);
587
588 env->CSR_MISC = 0;
589
590 env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, VS, 0);
591 env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, LIE, 0);
592
593 env->CSR_ESTAT = env->CSR_ESTAT & (~MAKE_64BIT_MASK(0, 2));
594 env->CSR_RVACFG = FIELD_DP64(env->CSR_RVACFG, CSR_RVACFG, RBITS, 0);
595 env->CSR_CPUID = cs->cpu_index;
596 env->CSR_TCFG = FIELD_DP64(env->CSR_TCFG, CSR_TCFG, EN, 0);
597 env->CSR_LLBCTL = FIELD_DP64(env->CSR_LLBCTL, CSR_LLBCTL, KLO, 0);
598 env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0);
599 env->CSR_MERRCTL = FIELD_DP64(env->CSR_MERRCTL, CSR_MERRCTL, ISMERR, 0);
600 env->CSR_TID = cs->cpu_index;
601 /*
602 * Workaround for edk2-stable202408, CSR PGD register is set only if
603 * its value is equal to zero for boot cpu, it causes reboot issue.
604 *
605 * Here clear CSR registers relative with TLB.
606 */
607 env->CSR_PGDH = 0;
608 env->CSR_PGDL = 0;
609 env->CSR_PWCH = 0;
610 env->CSR_EENTRY = 0;
611 env->CSR_TLBRENTRY = 0;
612 env->CSR_MERRENTRY = 0;
613 /* set CSR_PWCL.PTBASE and CSR_STLBPS.PS bits from CSR_PRCFG2 */
614 if (env->CSR_PRCFG2 == 0) {
615 env->CSR_PRCFG2 = 0x3fffff000;
616 }
617 tlb_ps = ctz32(env->CSR_PRCFG2);
618 env->CSR_STLBPS = FIELD_DP64(env->CSR_STLBPS, CSR_STLBPS, PS, tlb_ps);
619 env->CSR_PWCL = FIELD_DP64(env->CSR_PWCL, CSR_PWCL, PTBASE, tlb_ps);
620 for (n = 0; n < 4; n++) {
621 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV0, 0);
622 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV1, 0);
623 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV2, 0);
624 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV3, 0);
625 }
626
627 #ifndef CONFIG_USER_ONLY
628 env->pc = 0x1c000000;
629 #ifdef CONFIG_TCG
630 memset(env->tlb, 0, sizeof(env->tlb));
631 #endif
632 if (kvm_enabled()) {
633 kvm_arch_reset_vcpu(cs);
634 }
635 #endif
636
637 #ifdef CONFIG_TCG
638 restore_fp_status(env);
639 #endif
640 cs->exception_index = -1;
641 }
642
loongarch_cpu_disas_set_info(CPUState * s,disassemble_info * info)643 static void loongarch_cpu_disas_set_info(CPUState *s, disassemble_info *info)
644 {
645 info->endian = BFD_ENDIAN_LITTLE;
646 info->print_insn = print_insn_loongarch;
647 }
648
loongarch_cpu_realizefn(DeviceState * dev,Error ** errp)649 static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp)
650 {
651 CPUState *cs = CPU(dev);
652 LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(dev);
653 Error *local_err = NULL;
654
655 cpu_exec_realizefn(cs, &local_err);
656 if (local_err != NULL) {
657 error_propagate(errp, local_err);
658 return;
659 }
660
661 loongarch_cpu_register_gdb_regs_for_features(cs);
662
663 qemu_init_vcpu(cs);
664 cpu_reset(cs);
665
666 lacc->parent_realize(dev, errp);
667 }
668
loongarch_cpu_unrealizefn(DeviceState * dev)669 static void loongarch_cpu_unrealizefn(DeviceState *dev)
670 {
671 LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(dev);
672
673 #ifndef CONFIG_USER_ONLY
674 cpu_remove_sync(CPU(dev));
675 #endif
676
677 lacc->parent_unrealize(dev);
678 }
679
loongarch_get_lsx(Object * obj,Error ** errp)680 static bool loongarch_get_lsx(Object *obj, Error **errp)
681 {
682 return LOONGARCH_CPU(obj)->lsx != ON_OFF_AUTO_OFF;
683 }
684
loongarch_set_lsx(Object * obj,bool value,Error ** errp)685 static void loongarch_set_lsx(Object *obj, bool value, Error **errp)
686 {
687 LoongArchCPU *cpu = LOONGARCH_CPU(obj);
688 uint32_t val;
689
690 cpu->lsx = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
691 if (cpu->lsx == ON_OFF_AUTO_OFF) {
692 cpu->lasx = ON_OFF_AUTO_OFF;
693 if (cpu->lasx == ON_OFF_AUTO_ON) {
694 error_setg(errp, "Failed to disable LSX since LASX is enabled");
695 return;
696 }
697 }
698
699 if (kvm_enabled()) {
700 /* kvm feature detection in function kvm_arch_init_vcpu */
701 return;
702 }
703
704 /* LSX feature detection in TCG mode */
705 val = cpu->env.cpucfg[2];
706 if (cpu->lsx == ON_OFF_AUTO_ON) {
707 if (FIELD_EX32(val, CPUCFG2, LSX) == 0) {
708 error_setg(errp, "Failed to enable LSX in TCG mode");
709 return;
710 }
711 } else {
712 cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LASX, 0);
713 val = cpu->env.cpucfg[2];
714 }
715
716 cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LSX, value);
717 }
718
loongarch_get_lasx(Object * obj,Error ** errp)719 static bool loongarch_get_lasx(Object *obj, Error **errp)
720 {
721 return LOONGARCH_CPU(obj)->lasx != ON_OFF_AUTO_OFF;
722 }
723
loongarch_set_lasx(Object * obj,bool value,Error ** errp)724 static void loongarch_set_lasx(Object *obj, bool value, Error **errp)
725 {
726 LoongArchCPU *cpu = LOONGARCH_CPU(obj);
727 uint32_t val;
728
729 cpu->lasx = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
730 if ((cpu->lsx == ON_OFF_AUTO_OFF) && (cpu->lasx == ON_OFF_AUTO_ON)) {
731 error_setg(errp, "Failed to enable LASX since lSX is disabled");
732 return;
733 }
734
735 if (kvm_enabled()) {
736 /* kvm feature detection in function kvm_arch_init_vcpu */
737 return;
738 }
739
740 /* LASX feature detection in TCG mode */
741 val = cpu->env.cpucfg[2];
742 if (cpu->lasx == ON_OFF_AUTO_ON) {
743 if (FIELD_EX32(val, CPUCFG2, LASX) == 0) {
744 error_setg(errp, "Failed to enable LASX in TCG mode");
745 return;
746 }
747 }
748
749 cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LASX, value);
750 }
751
loongarch_cpu_post_init(Object * obj)752 void loongarch_cpu_post_init(Object *obj)
753 {
754 LoongArchCPU *cpu = LOONGARCH_CPU(obj);
755
756 cpu->lbt = ON_OFF_AUTO_OFF;
757 cpu->pmu = ON_OFF_AUTO_OFF;
758 cpu->lsx = ON_OFF_AUTO_AUTO;
759 cpu->lasx = ON_OFF_AUTO_AUTO;
760 object_property_add_bool(obj, "lsx", loongarch_get_lsx,
761 loongarch_set_lsx);
762 object_property_add_bool(obj, "lasx", loongarch_get_lasx,
763 loongarch_set_lasx);
764 /* lbt is enabled only in kvm mode, not supported in tcg mode */
765 if (kvm_enabled()) {
766 kvm_loongarch_cpu_post_init(cpu);
767 }
768 }
769
loongarch_cpu_init(Object * obj)770 static void loongarch_cpu_init(Object *obj)
771 {
772 #ifndef CONFIG_USER_ONLY
773 LoongArchCPU *cpu = LOONGARCH_CPU(obj);
774
775 qdev_init_gpio_in(DEVICE(cpu), loongarch_cpu_set_irq, N_IRQS);
776 #ifdef CONFIG_TCG
777 timer_init_ns(&cpu->timer, QEMU_CLOCK_VIRTUAL,
778 &loongarch_constant_timer_cb, cpu);
779 #endif
780 #endif
781 }
782
loongarch_cpu_class_by_name(const char * cpu_model)783 static ObjectClass *loongarch_cpu_class_by_name(const char *cpu_model)
784 {
785 ObjectClass *oc;
786
787 oc = object_class_by_name(cpu_model);
788 if (!oc) {
789 g_autofree char *typename
790 = g_strdup_printf(LOONGARCH_CPU_TYPE_NAME("%s"), cpu_model);
791 oc = object_class_by_name(typename);
792 }
793
794 return oc;
795 }
796
loongarch_cpu_dump_csr(CPUState * cs,FILE * f)797 static void loongarch_cpu_dump_csr(CPUState *cs, FILE *f)
798 {
799 #ifndef CONFIG_USER_ONLY
800 CPULoongArchState *env = cpu_env(cs);
801 CSRInfo *csr_info;
802 int64_t *addr;
803 int i, j, len, col = 0;
804
805 qemu_fprintf(f, "\n");
806
807 /* Dump all generic CSR register */
808 for (i = 0; i < LOONGARCH_CSR_DBG; i++) {
809 csr_info = get_csr(i);
810 if (!csr_info || (csr_info->flags & CSRFL_UNUSED)) {
811 if (i == (col + 3)) {
812 qemu_fprintf(f, "\n");
813 }
814
815 continue;
816 }
817
818 if ((i > (col + 3)) || (i == col)) {
819 col = i & ~3;
820 qemu_fprintf(f, " CSR%03d:", col);
821 }
822
823 addr = (void *)env + csr_info->offset;
824 qemu_fprintf(f, " %s ", csr_info->name);
825 len = strlen(csr_info->name);
826 for (; len < 6; len++) {
827 qemu_fprintf(f, " ");
828 }
829
830 qemu_fprintf(f, "%" PRIx64, *addr);
831 j = find_last_bit((void *)addr, BITS_PER_LONG) & (BITS_PER_LONG - 1);
832 len += j / 4 + 1;
833 for (; len < 22; len++) {
834 qemu_fprintf(f, " ");
835 }
836
837 if (i == (col + 3)) {
838 qemu_fprintf(f, "\n");
839 }
840 }
841 qemu_fprintf(f, "\n");
842 #endif
843 }
844
loongarch_cpu_dump_state(CPUState * cs,FILE * f,int flags)845 static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
846 {
847 CPULoongArchState *env = cpu_env(cs);
848 int i;
849
850 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
851 qemu_fprintf(f, " FCSR0 0x%08x\n", env->fcsr0);
852
853 /* gpr */
854 for (i = 0; i < 32; i++) {
855 if ((i & 3) == 0) {
856 qemu_fprintf(f, " GPR%02d:", i);
857 }
858 qemu_fprintf(f, " %s %016" PRIx64, regnames[i], env->gpr[i]);
859 if ((i & 3) == 3) {
860 qemu_fprintf(f, "\n");
861 }
862 }
863
864 /* csr */
865 loongarch_cpu_dump_csr(cs, f);
866
867 /* fpr */
868 if (flags & CPU_DUMP_FPU) {
869 for (i = 0; i < 32; i++) {
870 qemu_fprintf(f, " %s %016" PRIx64, fregnames[i], env->fpr[i].vreg.D(0));
871 if ((i & 3) == 3) {
872 qemu_fprintf(f, "\n");
873 }
874 }
875 }
876 }
877
878 #ifdef CONFIG_TCG
879 static const TCGCPUOps loongarch_tcg_ops = {
880 .guest_default_memory_order = 0,
881 .mttcg_supported = true,
882
883 .initialize = loongarch_translate_init,
884 .translate_code = loongarch_translate_code,
885 .get_tb_cpu_state = loongarch_get_tb_cpu_state,
886 .synchronize_from_tb = loongarch_cpu_synchronize_from_tb,
887 .restore_state_to_opc = loongarch_restore_state_to_opc,
888 .mmu_index = loongarch_cpu_mmu_index,
889
890 #ifndef CONFIG_USER_ONLY
891 .tlb_fill = loongarch_cpu_tlb_fill,
892 .cpu_exec_interrupt = loongarch_cpu_exec_interrupt,
893 .cpu_exec_halt = loongarch_cpu_has_work,
894 .cpu_exec_reset = cpu_reset,
895 .do_interrupt = loongarch_cpu_do_interrupt,
896 .do_transaction_failed = loongarch_cpu_do_transaction_failed,
897 #endif
898 };
899 #endif /* CONFIG_TCG */
900
901 #ifndef CONFIG_USER_ONLY
902 #include "hw/core/sysemu-cpu-ops.h"
903
904 static const struct SysemuCPUOps loongarch_sysemu_ops = {
905 .has_work = loongarch_cpu_has_work,
906 .write_elf64_note = loongarch_cpu_write_elf64_note,
907 .get_phys_page_debug = loongarch_cpu_get_phys_page_debug,
908 };
909
loongarch_cpu_get_arch_id(CPUState * cs)910 static int64_t loongarch_cpu_get_arch_id(CPUState *cs)
911 {
912 LoongArchCPU *cpu = LOONGARCH_CPU(cs);
913
914 return cpu->phy_id;
915 }
916 #endif
917
918 static const Property loongarch_cpu_properties[] = {
919 DEFINE_PROP_INT32("socket-id", LoongArchCPU, socket_id, 0),
920 DEFINE_PROP_INT32("core-id", LoongArchCPU, core_id, 0),
921 DEFINE_PROP_INT32("thread-id", LoongArchCPU, thread_id, 0),
922 DEFINE_PROP_INT32("node-id", LoongArchCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
923 };
924
loongarch_cpu_class_init(ObjectClass * c,const void * data)925 static void loongarch_cpu_class_init(ObjectClass *c, const void *data)
926 {
927 LoongArchCPUClass *lacc = LOONGARCH_CPU_CLASS(c);
928 CPUClass *cc = CPU_CLASS(c);
929 DeviceClass *dc = DEVICE_CLASS(c);
930 ResettableClass *rc = RESETTABLE_CLASS(c);
931
932 device_class_set_props(dc, loongarch_cpu_properties);
933 device_class_set_parent_realize(dc, loongarch_cpu_realizefn,
934 &lacc->parent_realize);
935 device_class_set_parent_unrealize(dc, loongarch_cpu_unrealizefn,
936 &lacc->parent_unrealize);
937 resettable_class_set_parent_phases(rc, NULL, loongarch_cpu_reset_hold, NULL,
938 &lacc->parent_phases);
939
940 cc->class_by_name = loongarch_cpu_class_by_name;
941 cc->dump_state = loongarch_cpu_dump_state;
942 cc->set_pc = loongarch_cpu_set_pc;
943 cc->get_pc = loongarch_cpu_get_pc;
944 #ifndef CONFIG_USER_ONLY
945 cc->get_arch_id = loongarch_cpu_get_arch_id;
946 dc->vmsd = &vmstate_loongarch_cpu;
947 cc->sysemu_ops = &loongarch_sysemu_ops;
948 #endif
949 cc->disas_set_info = loongarch_cpu_disas_set_info;
950 cc->gdb_read_register = loongarch_cpu_gdb_read_register;
951 cc->gdb_write_register = loongarch_cpu_gdb_write_register;
952 cc->gdb_stop_before_watchpoint = true;
953
954 #ifdef CONFIG_TCG
955 cc->tcg_ops = &loongarch_tcg_ops;
956 #endif
957 dc->user_creatable = true;
958 }
959
loongarch32_gdb_arch_name(CPUState * cs)960 static const gchar *loongarch32_gdb_arch_name(CPUState *cs)
961 {
962 return "loongarch32";
963 }
964
loongarch32_cpu_class_init(ObjectClass * c,const void * data)965 static void loongarch32_cpu_class_init(ObjectClass *c, const void *data)
966 {
967 CPUClass *cc = CPU_CLASS(c);
968
969 cc->gdb_core_xml_file = "loongarch-base32.xml";
970 cc->gdb_arch_name = loongarch32_gdb_arch_name;
971 }
972
loongarch64_gdb_arch_name(CPUState * cs)973 static const gchar *loongarch64_gdb_arch_name(CPUState *cs)
974 {
975 return "loongarch64";
976 }
977
loongarch64_cpu_class_init(ObjectClass * c,const void * data)978 static void loongarch64_cpu_class_init(ObjectClass *c, const void *data)
979 {
980 CPUClass *cc = CPU_CLASS(c);
981
982 cc->gdb_core_xml_file = "loongarch-base64.xml";
983 cc->gdb_arch_name = loongarch64_gdb_arch_name;
984 }
985
986 #define DEFINE_LOONGARCH_CPU_TYPE(size, model, initfn) \
987 { \
988 .parent = TYPE_LOONGARCH##size##_CPU, \
989 .instance_init = initfn, \
990 .name = LOONGARCH_CPU_TYPE_NAME(model), \
991 }
992
993 static const TypeInfo loongarch_cpu_type_infos[] = {
994 {
995 .name = TYPE_LOONGARCH_CPU,
996 .parent = TYPE_CPU,
997 .instance_size = sizeof(LoongArchCPU),
998 .instance_align = __alignof(LoongArchCPU),
999 .instance_init = loongarch_cpu_init,
1000
1001 .abstract = true,
1002 .class_size = sizeof(LoongArchCPUClass),
1003 .class_init = loongarch_cpu_class_init,
1004 },
1005 {
1006 .name = TYPE_LOONGARCH32_CPU,
1007 .parent = TYPE_LOONGARCH_CPU,
1008
1009 .abstract = true,
1010 .class_init = loongarch32_cpu_class_init,
1011 },
1012 {
1013 .name = TYPE_LOONGARCH64_CPU,
1014 .parent = TYPE_LOONGARCH_CPU,
1015
1016 .abstract = true,
1017 .class_init = loongarch64_cpu_class_init,
1018 },
1019 DEFINE_LOONGARCH_CPU_TYPE(64, "la464", loongarch_la464_initfn),
1020 DEFINE_LOONGARCH_CPU_TYPE(32, "la132", loongarch_la132_initfn),
1021 DEFINE_LOONGARCH_CPU_TYPE(64, "max", loongarch_max_initfn),
1022 };
1023
1024 DEFINE_TYPES(loongarch_cpu_type_infos)
1025