Searched hist:e844ca0cf5f4d7dbd09dcd24de45b8aea46d30cc (Results 1 – 5 of 5) sorted by relevance
/kvm-unit-tests/riscv/ |
H A D | isa-dbltrp.c | e844ca0cf5f4d7dbd09dcd24de45b8aea46d30cc Mon Jun 16 11:59:00 UTC 2025 Clément Léger <cleger@rivosinc.com> riscv: Add ISA double trap extension testing
This test allows to test the double trap implementation of hardware as well as the SBI FWFT and SSE support for double trap. The tests will try to trigger double trap using various sequences and will test to receive the SSE double trap event if supported.
It is provided as a separate test from the SBI one for two reasons: - It isn't specifically testing SBI "per se". - It ends up by trying to crash into in M-mode.
Currently, the test uses a page fault to raise a trap programatically. Some concern was raised by a github user on the original branch [1] saying that the spec doesn't mandate any trap to be delegatable and that we would need a way to detect which ones are delegatable. I think we can safely assume that PAGE FAULT is delegatable and if a hardware that does not have support comes up then it will probably be the vendor responsibility to provide a way to do so.
Link: https://github.com/clementleger/kvm-unit-tests/issues/1 [1] Signed-off-by: Clément Léger <cleger@rivosinc.com> Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
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H A D | unittests.cfg | e844ca0cf5f4d7dbd09dcd24de45b8aea46d30cc Mon Jun 16 11:59:00 UTC 2025 Clément Léger <cleger@rivosinc.com> riscv: Add ISA double trap extension testing
This test allows to test the double trap implementation of hardware as well as the SBI FWFT and SSE support for double trap. The tests will try to trigger double trap using various sequences and will test to receive the SSE double trap event if supported.
It is provided as a separate test from the SBI one for two reasons: - It isn't specifically testing SBI "per se". - It ends up by trying to crash into in M-mode.
Currently, the test uses a page fault to raise a trap programatically. Some concern was raised by a github user on the original branch [1] saying that the spec doesn't mandate any trap to be delegatable and that we would need a way to detect which ones are delegatable. I think we can safely assume that PAGE FAULT is delegatable and if a hardware that does not have support comes up then it will probably be the vendor responsibility to provide a way to do so.
Link: https://github.com/clementleger/kvm-unit-tests/issues/1 [1] Signed-off-by: Clément Léger <cleger@rivosinc.com> Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
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H A D | Makefile | e844ca0cf5f4d7dbd09dcd24de45b8aea46d30cc Mon Jun 16 11:59:00 UTC 2025 Clément Léger <cleger@rivosinc.com> riscv: Add ISA double trap extension testing
This test allows to test the double trap implementation of hardware as well as the SBI FWFT and SSE support for double trap. The tests will try to trigger double trap using various sequences and will test to receive the SSE double trap event if supported.
It is provided as a separate test from the SBI one for two reasons: - It isn't specifically testing SBI "per se". - It ends up by trying to crash into in M-mode.
Currently, the test uses a page fault to raise a trap programatically. Some concern was raised by a github user on the original branch [1] saying that the spec doesn't mandate any trap to be delegatable and that we would need a way to detect which ones are delegatable. I think we can safely assume that PAGE FAULT is delegatable and if a hardware that does not have support comes up then it will probably be the vendor responsibility to provide a way to do so.
Link: https://github.com/clementleger/kvm-unit-tests/issues/1 [1] Signed-off-by: Clément Léger <cleger@rivosinc.com> Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
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/kvm-unit-tests/lib/riscv/asm/ |
H A D | processor.h | e844ca0cf5f4d7dbd09dcd24de45b8aea46d30cc Mon Jun 16 11:59:00 UTC 2025 Clément Léger <cleger@rivosinc.com> riscv: Add ISA double trap extension testing
This test allows to test the double trap implementation of hardware as well as the SBI FWFT and SSE support for double trap. The tests will try to trigger double trap using various sequences and will test to receive the SSE double trap event if supported.
It is provided as a separate test from the SBI one for two reasons: - It isn't specifically testing SBI "per se". - It ends up by trying to crash into in M-mode.
Currently, the test uses a page fault to raise a trap programatically. Some concern was raised by a github user on the original branch [1] saying that the spec doesn't mandate any trap to be delegatable and that we would need a way to detect which ones are delegatable. I think we can safely assume that PAGE FAULT is delegatable and if a hardware that does not have support comes up then it will probably be the vendor responsibility to provide a way to do so.
Link: https://github.com/clementleger/kvm-unit-tests/issues/1 [1] Signed-off-by: Clément Léger <cleger@rivosinc.com> Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
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H A D | csr.h | e844ca0cf5f4d7dbd09dcd24de45b8aea46d30cc Mon Jun 16 11:59:00 UTC 2025 Clément Léger <cleger@rivosinc.com> riscv: Add ISA double trap extension testing
This test allows to test the double trap implementation of hardware as well as the SBI FWFT and SSE support for double trap. The tests will try to trigger double trap using various sequences and will test to receive the SSE double trap event if supported.
It is provided as a separate test from the SBI one for two reasons: - It isn't specifically testing SBI "per se". - It ends up by trying to crash into in M-mode.
Currently, the test uses a page fault to raise a trap programatically. Some concern was raised by a github user on the original branch [1] saying that the spec doesn't mandate any trap to be delegatable and that we would need a way to detect which ones are delegatable. I think we can safely assume that PAGE FAULT is delegatable and if a hardware that does not have support comes up then it will probably be the vendor responsibility to provide a way to do so.
Link: https://github.com/clementleger/kvm-unit-tests/issues/1 [1] Signed-off-by: Clément Léger <cleger@rivosinc.com> Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
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