Merge branch 'riscv/sbi' into 'master'

riscv: Fixes and more tests

See merge request kvm-unit-tests/kvm-unit-tests!78

riscv: Add ISA double trap extension testing

This test allows to test the double trap implementation of hardware as
well as the SBI FWFT and SSE support for double trap. The tests will try
to trigge

riscv: Add ISA double trap extension testing

This test allows to test the double trap implementation of hardware as
well as the SBI FWFT and SSE support for double trap. The tests will try
to trigger double trap using various sequences and will test to receive
the SSE double trap event if supported.

It is provided as a separate test from the SBI one for two reasons:
- It isn't specifically testing SBI "per se".
- It ends up by trying to crash into in M-mode.

Currently, the test uses a page fault to raise a trap programatically.
Some concern was raised by a github user on the original branch [1]
saying that the spec doesn't mandate any trap to be delegatable and that
we would need a way to detect which ones are delegatable. I think we can
safely assume that PAGE FAULT is delegatable and if a hardware that does
not have support comes up then it will probably be the vendor
responsibility to provide a way to do so.

Link: https://github.com/clementleger/kvm-unit-tests/issues/1 [1]
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Signed-off-by: Andrew Jones <andrew.jones@linux.dev>

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riscv: Add RV_INSN_LEN to processor.h

When handling traps and faults it is often necessary to know the size
of the instruction at epc. Add RV_INSN_LEN to calculate the
instruction size.

Signed-off-

riscv: Add RV_INSN_LEN to processor.h

When handling traps and faults it is often necessary to know the size
of the instruction at epc. Add RV_INSN_LEN to calculate the
instruction size.

Signed-off-by: Jesse Taube <jesse@rivosinc.com>
Signed-off-by: Andrew Jones <andrew.jones@linux.dev>

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Merge branch 'riscv/queue' into 'master'

lib/on-cpus and riscv smp improvements

See merge request kvm-unit-tests/kvm-unit-tests!69

riscv: Rework smp_boot_secondary

Use HSM status to determine when a secondary should be started.
Also save the stack pointer so a secondary may be stopped and
started again without leaking old stack

riscv: Rework smp_boot_secondary

Use HSM status to determine when a secondary should be started.
Also save the stack pointer so a secondary may be stopped and
started again without leaking old stacks.

Signed-off-by: Andrew Jones <andrew.jones@linux.dev>

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Merge branch 'riscv/sbi' into 'master'

riscv: Add support for SBI tests

See merge request kvm-unit-tests/kvm-unit-tests!67

riscv: Provide helpers for IPIs

Provide a few functions to enable/disable/acknowledge IPIs.

Signed-off-by: Andrew Jones <andrew.jones@linux.dev>

riscv: Introduce local_hart_init

When Sstc is available make sure that even if we enable timer
interrupts nothing will happen. This is necessary for cases where
the unit tests actually intend to use

riscv: Introduce local_hart_init

When Sstc is available make sure that even if we enable timer
interrupts nothing will happen. This is necessary for cases where
the unit tests actually intend to use the SBI TIME extension and
aren't thinking about Sstc at all, like the SBI TIME test in
riscv/sbi where we can now remove the initialization.

We introduce local_hart_init() rather than something like
local_timer_init() for this since other non-timer-related CSRs will
also need to be set at init time in the future and we can just lump
them all together.

Signed-off-by: Andrew Jones <andrew.jones@linux.dev>

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Merge branch 'riscv/sbi' into 'master'

riscv: Add TIME SBI extension tests

See merge request kvm-unit-tests/kvm-unit-tests!62

riscv: Update exception cause list

Update the list of exception and interrupt causes to follow the latest
RISC-V privileged ISA specification (version 20240411 section 18.6.1).

Reviewed-by: Andrew

riscv: Update exception cause list

Update the list of exception and interrupt causes to follow the latest
RISC-V privileged ISA specification (version 20240411 section 18.6.1).

Reviewed-by: Andrew Jones <andrew.jones@linux.dev>
Signed-off-by: James Raphael Tiovalen <jamestiotio@gmail.com>
Signed-off-by: Andrew Jones <andrew.jones@linux.dev>

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riscv: Extend exception handling support for interrupts

Add install_irq_handler() to enable tests to install interrupt handlers.
Also add local_irq_enable() and local_irq_disable() to respectively
e

riscv: Extend exception handling support for interrupts

Add install_irq_handler() to enable tests to install interrupt handlers.
Also add local_irq_enable() and local_irq_disable() to respectively
enable and disable IRQs via the sstatus.SIE bit.

Signed-off-by: James Raphael Tiovalen <jamestiotio@gmail.com>
Signed-off-by: Andrew Jones <andrew.jones@linux.dev>

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Merge branch 'riscv/initial-port-v3' into 'master'

riscv: Initial port

See merge request kvm-unit-tests/kvm-unit-tests!50

riscv: Add isa string parsing

We can probably get away with just assuming several important
and popular extensions (at least everything covered by G), but
we'll also want to use some extensions whic

riscv: Add isa string parsing

We can probably get away with just assuming several important
and popular extensions (at least everything covered by G), but
we'll also want to use some extensions which we should ensure
are present by parsing the isa string. Add a parser and already
apply it to Sstc.

Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
Acked-by: Thomas Huth <thuth@redhat.com>

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riscv: Add exception handling

Steal more code from Linux to implement exception handling, but with
the same kvm-unit-tests API that Arm has. Also introduce struct
thread_info like Arm has in order t

riscv: Add exception handling

Steal more code from Linux to implement exception handling, but with
the same kvm-unit-tests API that Arm has. Also introduce struct
thread_info like Arm has in order to hold the handler pointers.
Finally, as usual, extend the selftest to make sure it all works.

Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
Acked-by: Thomas Huth <thuth@redhat.com>

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