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Searched full:xo (Results 1 – 6 of 6) sorted by relevance

/qemu/target/i386/tcg/
H A Dtcg-cpu.c195 #define XO(bit, field) \ in x86_tcg_cpu_xsave_init() macro
198 XO(XSTATE_FP_BIT, legacy); in x86_tcg_cpu_xsave_init()
199 XO(XSTATE_SSE_BIT, legacy); in x86_tcg_cpu_xsave_init()
200 XO(XSTATE_YMM_BIT, avx_state); in x86_tcg_cpu_xsave_init()
201 XO(XSTATE_BNDREGS_BIT, bndreg_state); in x86_tcg_cpu_xsave_init()
202 XO(XSTATE_BNDCSR_BIT, bndcsr_state); in x86_tcg_cpu_xsave_init()
203 XO(XSTATE_OPMASK_BIT, opmask_state); in x86_tcg_cpu_xsave_init()
204 XO(XSTATE_ZMM_Hi256_BIT, zmm_hi256_state); in x86_tcg_cpu_xsave_init()
205 XO(XSTATE_Hi16_ZMM_BIT, hi16_zmm_state); in x86_tcg_cpu_xsave_init()
206 XO(XSTATE_PKRU_BIT, pkru_state); in x86_tcg_cpu_xsave_init()
[all …]
H A Dfpu_helper.c2588 #define XO(X) offsetof(X86XSaveArea, X) macro
2602 access_stw(ac, ptr + XO(legacy.fcw), env->fpuc); in do_xsave_fpu()
2603 access_stw(ac, ptr + XO(legacy.fsw), fpus); in do_xsave_fpu()
2604 access_stw(ac, ptr + XO(legacy.ftw), fptag ^ 0xff); in do_xsave_fpu()
2609 access_stq(ac, ptr + XO(legacy.fpip), 0); /* eip+sel; rip */ in do_xsave_fpu()
2610 access_stq(ac, ptr + XO(legacy.fpdp), 0); /* edp+sel; rdp */ in do_xsave_fpu()
2612 addr = ptr + XO(legacy.fpregs); in do_xsave_fpu()
2626 access_stl(ac, ptr + XO(legacy.mxcsr), env->mxcsr); in do_xsave_mxcsr()
2627 access_stl(ac, ptr + XO(legacy.mxcsr_mask), 0x0000ffff); in do_xsave_mxcsr()
2642 addr = ptr + XO(legacy.xmm_regs); in do_xsave_sse()
[all …]
/qemu/target/ppc/
H A Dinsn32.decode211 &XO rt ra rb oe:bool rc:bool
212 @XO ...... rt:5 ra:5 rb:5 oe:1 ......... rc:1 &XO
371 ADD 011111 ..... ..... ..... . 100001010 . @XO
372 ADDC 011111 ..... ..... ..... . 000001010 . @XO
373 ADDE 011111 ..... ..... ..... . 010001010 . @XO
388 SUBF 011111 ..... ..... ..... . 000101000 . @XO
390 SUBFC 011111 ..... ..... ..... . 000001000 . @XO
391 SUBFE 011111 ..... ..... ..... . 010001000 . @XO
402 DIVW 011111 ..... ..... ..... . 111101011 . @XO
403 DIVWU 011111 ..... ..... ..... . 111001011 . @XO
[all …]
/qemu/tcg/i386/
H A Dtcg-target-con-set.h54 C_O1_I4(x, x, x, xO, x)
H A Dtcg-target.c.inc4213 return C_O1_I4(x, x, x, xO, x);
/qemu/target/ppc/translate/
H A Dfp-impl.c.inc516 * with OPCD=63 and XO=583 should be decoded as MFFS.