Merge tag 'pull-tcg-20250429' of https://gitlab.com/rth7680/qemu into staging

Convert TCG backend code generators to TCGOutOp structures,
decomposing the monolithic tcg_out_op functions.

# -----BEG

Merge tag 'pull-tcg-20250429' of https://gitlab.com/rth7680/qemu into staging

Convert TCG backend code generators to TCGOutOp structures,
decomposing the monolithic tcg_out_op functions.

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# gpg: Signature made Tue 29 Apr 2025 13:36:07 EDT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F

* tag 'pull-tcg-20250429' of https://gitlab.com/rth7680/qemu: (161 commits)
tcg/sparc64: Implement CTPOP
tcg/sparc64: Unexport use_vis3_instructions
tcg: Remove tcg_out_op
tcg: Convert qemu_st{2} to TCGOutOpLdSt{2}
tcg: Convert qemu_ld{2} to TCGOutOpLoad{2}
tcg: Merge INDEX_op_{ld,st}_{i32,i64,i128}
tcg: Remove INDEX_op_qemu_st8_*
tcg: Stash MemOp size in TCGOP_FLAGS
tcg: Merge INDEX_op_st*_{i32,i64}
tcg: Convert st to TCGOutOpStore
tcg: Merge INDEX_op_ld*_{i32,i64}
tcg: Convert ld to TCGOutOpLoad
tcg: Formalize tcg_out_goto_ptr
tcg: Formalize tcg_out_br
tcg: Formalize tcg_out_mb
tcg: Remove add2/sub2 opcodes
tcg/tci: Implement add/sub carry opcodes
tcg/sparc64: Implement add/sub carry opcodes
tcg/sparc64: Hoist tcg_cond_to_bcond lookup out of tcg_out_movcc
tcg/s390x: Use ADD LOGICAL WITH SIGNED IMMEDIATE
...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>

show more ...

tcg/i386: Special case addci r, 0, 0

Using addci with two zeros as input in order to capture the value
of the carry-in bit is common. Special case this with sbb+neg so
that we do not have to load 0

tcg/i386: Special case addci r, 0, 0

Using addci with two zeros as input in order to capture the value
of the carry-in bit is common. Special case this with sbb+neg so
that we do not have to load 0 into a register first.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

tcg/i386: Implement add/sub carry opcodes

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

tcg: Convert andc to TCGOutOpBinary

At the same time, drop all backend support for immediate
operands, as we now transform andc to and during optimize.

Reviewed-by: Philippe Mathieu-Daudé <philmd@l

tcg: Convert andc to TCGOutOpBinary

At the same time, drop all backend support for immediate
operands, as we now transform andc to and during optimize.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Merge tag 'pull-tcg-20240922' of https://gitlab.com/rth7680/qemu into staging

target/ppc: Fix lxvx/stxvx facility check
linux-user: update syscall_nr.h to Linux v6.10
linux-user: update syscall.tbl

Merge tag 'pull-tcg-20240922' of https://gitlab.com/rth7680/qemu into staging

target/ppc: Fix lxvx/stxvx facility check
linux-user: update syscall_nr.h to Linux v6.10
linux-user: update syscall.tbl to Linux v6.11
tcg: Fix iteration step in 32-bit gvec operation
tcg: Propagate new TCGOp to add_as_label_use
tcg/*: Do not expand cmp_vec, cmpsel_vec early
tcg/optimize: Fold movcond with true and false values identical
tcg/optimize: Optimize cmp_vec and cmpsel_vec
tcg/optimize: Optimize bitsel_vec
tcg/i386: Optimize cmpsel with constant 0 operand 3.
tcg/i386: Implement cmp_vec with avx512 insns
tcg/i386: Implement cmpsel_vec with avx512 insns
tcg/i386: Implement vector TST{EQ,NE} for avx512
tcg/ppc: Implement cmpsel_vec and optimize with constant 0/-1 arguments
tcg/s390x: Implement cmpsel_vec and optimize with constant 0/-1 arguments

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# gpg: Signature made Sun 22 Sep 2024 13:00:02 BST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F

* tag 'pull-tcg-20240922' of https://gitlab.com/rth7680/qemu: (31 commits)
linux-user: update syscall.tbl to Linux v6.11
linux-user,loongarch: move to syscalltbl file
linux-user,hexagon: move to syscalltbl file
linux-user,riscv: move to syscalltbl file
linux-user,openrisc: move to syscalltbl file
linux-user,aarch64: move to syscalltbl file
linux-user: update syscall.tbl to Linux v6.10
linux-user, mips: update syscall-args-o32.c.inc to Linux v6.10
linux-user: update syscall_nr.h to Linux v6.10
target/ppc: Fix lxvx/stxvx facility check
tcg/s390x: Optimize cmpsel with constant 0/-1 arguments
tcg/s390x: Implement cmpsel_vec
tcg/ppc: Optimize cmpsel with constant 0/-1 arguments
tcg/ppc: Implement cmpsel_vec
tcg/i386: Implement vector TST{EQ,NE} for avx512
tcg/i386: Implement cmpsel_vec with avx512 insns
tcg/i386: Add predicate parameters to tcg_out_evex_opc
tcg/i386: Implement cmp_vec with avx512 insns
tcg/i386: Optimize cmpsel with constant 0 operand 3.
tcg/optimize: Optimize bitsel_vec
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

tcg/i386: Optimize cmpsel with constant 0 operand 3.

These can be simplified to and/andc, avoiding the load of
the zero into a register.

Signed-off-by: Richard Henderson <richard.henderson@linaro.o

tcg/i386: Optimize cmpsel with constant 0 operand 3.

These can be simplified to and/andc, avoiding the load of
the zero into a register.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

tcg/i386: Do not expand cmpsel_vec early

Expand during output instead of during opcode generation.
Remove x86_vpblendvb_vec opcode, this this removes the only user.

Signed-off-by: Richard Henderson

tcg/i386: Do not expand cmpsel_vec early

Expand during output instead of during opcode generation.
Remove x86_vpblendvb_vec opcode, this this removes the only user.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Merge tag 'pull-tcg-20240205-2' of https://gitlab.com/rth7680/qemu into staging

tcg: Introduce TCG_COND_TST{EQ,NE}
target/alpha: Use TCG_COND_TST{EQ,NE}
target/m68k: Use TCG_COND_TST{EQ,NE} in gen_f

Merge tag 'pull-tcg-20240205-2' of https://gitlab.com/rth7680/qemu into staging

tcg: Introduce TCG_COND_TST{EQ,NE}
target/alpha: Use TCG_COND_TST{EQ,NE}
target/m68k: Use TCG_COND_TST{EQ,NE} in gen_fcc_cond
target/sparc: Use TCG_COND_TSTEQ in gen_op_mulscc
target/s390x: Use TCG_COND_TSTNE for CC_OP_{TM,ICM}
target/s390x: Improve general case of disas_jcc

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# gpg: Signature made Tue 06 Feb 2024 03:19:12 GMT
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# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F

* tag 'pull-tcg-20240205-2' of https://gitlab.com/rth7680/qemu: (39 commits)
tcg/tci: Support TCG_COND_TST{EQ,NE}
tcg/s390x: Support TCG_COND_TST{EQ,NE}
tcg/s390x: Add TCG_CT_CONST_CMP
tcg/s390x: Split constraint A into J+U
tcg/ppc: Support TCG_COND_TST{EQ,NE}
tcg/ppc: Add TCG_CT_CONST_CMP
tcg/ppc: Tidy up tcg_target_const_match
tcg/ppc: Use cr0 in tcg_to_bc and tcg_to_isel
tcg/ppc: Sink tcg_to_bc usage into tcg_out_bc
tcg/sparc64: Support TCG_COND_TST{EQ,NE}
tcg/sparc64: Pass TCGCond to tcg_out_cmp
tcg/sparc64: Hoist read of tcg_cond_to_rcond
tcg/i386: Use TEST r,r to test 8/16/32 bits
tcg/i386: Improve TSTNE/TESTEQ vs powers of two
tcg/i386: Support TCG_COND_TST{EQ,NE}
tcg/i386: Move tcg_cond_to_jcc[] into tcg_out_cmp
tcg/i386: Pass x86 condition codes to tcg_out_cmov
tcg/arm: Support TCG_COND_TST{EQ,NE}
tcg/arm: Split out tcg_out_cmp()
tcg/aarch64: Generate CBNZ for TSTNE of UINT32_MAX
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

tcg/i386: Improve TSTNE/TESTEQ vs powers of two

Use "test x,x" when the bit is one of the 4 sign bits.
Use "bt imm,x" otherwise.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Merge tag 'pull-tcg-20230823-2' of https://gitlab.com/rth7680/qemu into staging

accel/*: Widen pc/saved_insn for *_sw_breakpoint
accel/tcg: Replace remaining target_ulong in system-mode accel
tcg: s

Merge tag 'pull-tcg-20230823-2' of https://gitlab.com/rth7680/qemu into staging

accel/*: Widen pc/saved_insn for *_sw_breakpoint
accel/tcg: Replace remaining target_ulong in system-mode accel
tcg: spelling fixes
tcg: Document bswap, hswap, wswap byte patterns
tcg: Introduce negsetcond opcodes
tcg: Fold deposit with zero to and
tcg: Unify TCG_TARGET_HAS_extr[lh]_i64_i32
tcg/i386: Drop BYTEH deposits for 64-bit
tcg/i386: Allow immediate as input to deposit
target/*: Use tcg_gen_negsetcond_*

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# gpg: Signature made Thu 24 Aug 2023 14:27:10 EDT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F

* tag 'pull-tcg-20230823-2' of https://gitlab.com/rth7680/qemu: (48 commits)
tcg: spelling fixes
docs/devel/tcg-ops: fix missing newlines in "Host vector operations"
target/cris: Fix a typo in gen_swapr()
tcg/tcg-op: Document wswap_i64() byte pattern
tcg/tcg-op: Document hswap_i32/64() byte pattern
tcg/tcg-op: Document bswap64_i64() byte pattern
tcg/tcg-op: Document bswap32_i64() byte pattern
tcg/tcg-op: Document bswap32_i32() byte pattern
tcg/tcg-op: Document bswap16_i64() byte pattern
tcg/tcg-op: Document bswap16_i32() byte pattern
tcg/i386: Implement negsetcond_*
tcg/i386: Use shift in tcg_out_setcond
tcg/i386: Clear dest first in tcg_out_setcond if possible
tcg/i386: Use CMP+SBB in tcg_out_setcond
tcg/i386: Merge tcg_out_movcond{32,64}
tcg/i386: Merge tcg_out_setcond{32,64}
tcg/i386: Merge tcg_out_brcond{32,64}
tcg/sparc64: Implement negsetcond_*
tcg/s390x: Implement negsetcond_*
tcg/riscv: Implement negsetcond_*
...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>

show more ...

tcg/i386: Allow immediate as input to deposit_*

We can use MOVB and MOVW with an immediate just as easily
as with a register input.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-

tcg/i386: Allow immediate as input to deposit_*

We can use MOVB and MOVW with an immediate just as easily
as with a register input.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

tcg/i386: Drop BYTEH deposits for 64-bit

It is more useful to allow low-part deposits into all registers
than to restrict allocation for high-byte deposits.

Reviewed-by: Peter Maydell <peter.maydel

tcg/i386: Drop BYTEH deposits for 64-bit

It is more useful to allow low-part deposits into all registers
than to restrict allocation for high-byte deposits.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Merge tag 'pull-tcg-20230724' of https://gitlab.com/rth7680/qemu into staging

accel/tcg: Zero-pad vaddr in tlb debug output
accel/tcg: Fix type of 'last' for pageflags_{find,next}
accel/tcg: Fix sen

Merge tag 'pull-tcg-20230724' of https://gitlab.com/rth7680/qemu into staging

accel/tcg: Zero-pad vaddr in tlb debug output
accel/tcg: Fix type of 'last' for pageflags_{find,next}
accel/tcg: Fix sense of read-only probes in ldst_atomicity
accel/tcg: Take mmap_lock in load_atomic*_or_exit
tcg: Add earlyclobber to op_add2 for x86 and s390x
tcg/ppc: Fix race in goto_tb implementation

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# gpg: Signature made Mon 24 Jul 2023 09:52:07 BST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F

* tag 'pull-tcg-20230724' of https://gitlab.com/rth7680/qemu:
accel/tcg: Fix type of 'last' for pageflags_{find,next}
accel/tcg: Zero-pad vaddr in tlb_debug output
tcg/{i386, s390x}: Add earlyclobber to the op_add2's first output
accel/tcg: Take mmap_lock in load_atomic*_or_exit
accel/tcg: Fix sense of read-only probes in ldst_atomicity
include/exec: Add WITH_MMAP_LOCK_GUARD
tcg/ppc: Fix race in goto_tb implementation

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

tcg/{i386, s390x}: Add earlyclobber to the op_add2's first output

i386 and s390x implementations of op_add2 require an earlyclobber,
which is currently missing. This breaks VCKSM in s390x guests. E.

tcg/{i386, s390x}: Add earlyclobber to the op_add2's first output

i386 and s390x implementations of op_add2 require an earlyclobber,
which is currently missing. This breaks VCKSM in s390x guests. E.g., on
x86_64 the following op:

add2_i32 tmp2,tmp3,tmp2,tmp3,tmp3,tmp2 dead: 0 2 3 4 5 pref=none,0xffff

is translated to:

addl %ebx, %r12d
adcl %r12d, %ebx

Introduce a new C_N1_O1_I4 constraint, and make sure that earlyclobber
of aliased outputs is honored.

Cc: qemu-stable@nongnu.org
Fixes: 82790a870992 ("tcg: Add markup for output requires new register")
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230719221310.1968845-7-iii@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20220304' into staging

Reorder do_constant_folding_cond test to satisfy valgrind.
Fix value of MAX_OPC_PARAM_IARGS.
Add opcodes for vec

Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20220304' into staging

Reorder do_constant_folding_cond test to satisfy valgrind.
Fix value of MAX_OPC_PARAM_IARGS.
Add opcodes for vector nand, nor, eqv.
Support vector nand, nor, eqv on PPC and S390X hosts.
Support AVX512VL, AVX512BW, AVX512DQ, and AVX512VBMI2.

# gpg: Signature made Fri 04 Mar 2022 18:59:08 GMT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F

* remotes/rth-gitlab/tags/pull-tcg-20220304: (21 commits)
tcg/i386: Implement bitsel for avx512
tcg/i386: Implement more logical operations for avx512
tcg/i386: Implement avx512 multiply
tcg/i386: Implement avx512 min/max/abs
tcg/i386: Expand scalar rotate with avx512 insns
tcg/i386: Remove rotls_vec from tcg_target_op_def
tcg/i386: Expand vector word rotate as avx512vbmi2 shift-double
tcg/i386: Support avx512vbmi2 vector shift-double instructions
tcg/i386: Implement avx512 variable rotate
tcg/i386: Implement avx512 immediate rotate
tcg/i386: Implement avx512 immediate sari shift
tcg/i386: Implement avx512 scalar shift
tcg/i386: Implement avx512 variable shifts
tcg/i386: Use tcg_can_emit_vec_op in expand_vec_cmp_noinv
tcg/i386: Add tcg_out_evex_opc
tcg/i386: Detect AVX512
tcg/s390x: Implement vector NAND, NOR, EQV
tcg/ppc: Implement vector NAND, NOR, EQV
tcg: Add opcodes for vector nand, nor, eqv
tcg: Set MAX_OPC_PARAM_IARGS to 7
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

tcg/i386: Support avx512vbmi2 vector shift-double instructions

We will use VPSHLD, VPSHLDV and VPSHRDV for 16-bit rotates.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <

tcg/i386: Support avx512vbmi2 vector shift-double instructions

We will use VPSHLD, VPSHLDV and VPSHRDV for 16-bit rotates.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

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Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210202' into staging

TCG backend constraints cleanup

# gpg: Signature made Tue 02 Feb 2021 22:59:19 GMT
# gpg: using

Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210202' into staging

TCG backend constraints cleanup

# gpg: Signature made Tue 02 Feb 2021 22:59:19 GMT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F

* remotes/rth-gitlab/tags/pull-tcg-20210202: (24 commits)
tcg: Remove TCG_TARGET_CON_SET_H
tcg/tci: Split out constraint sets to tcg-target-con-set.h
tcg/sparc: Split out constraint sets to tcg-target-con-set.h
tcg/s390: Split out constraint sets to tcg-target-con-set.h
tcg/riscv: Split out constraint sets to tcg-target-con-set.h
tcg/ppc: Split out constraint sets to tcg-target-con-set.h
tcg/mips: Split out constraint sets to tcg-target-con-set.h
tcg/arm: Split out constraint sets to tcg-target-con-set.h
tcg/aarch64: Split out constraint sets to tcg-target-con-set.h
tcg/i386: Split out constraint sets to tcg-target-con-set.h
tcg: Remove TCG_TARGET_CON_STR_H
tcg/sparc: Split out target constraints to tcg-target-con-str.h
tcg/s390: Split out target constraints to tcg-target-con-str.h
tcg/riscv: Split out target constraints to tcg-target-con-str.h
tcg/mips: Split out target constraints to tcg-target-con-str.h
tcg/tci: Split out target constraints to tcg-target-con-str.h
tcg/ppc: Split out target constraints to tcg-target-con-str.h
tcg/aarch64: Split out target constraints to tcg-target-con-str.h
tcg/arm: Split out target constraints to tcg-target-con-str.h
tcg/i386: Split out target constraints to tcg-target-con-str.h
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

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tcg/i386: Split out constraint sets to tcg-target-con-set.h

This exports the constraint sets from tcg_target_op_def to
a place we will be able to manipulate more in future.

Reviewed-by: Peter Mayde

tcg/i386: Split out constraint sets to tcg-target-con-set.h

This exports the constraint sets from tcg_target_op_def to
a place we will be able to manipulate more in future.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...