Home
last modified time | relevance | path

Searched +full:uart +full:- +full:fifosize (Results 1 – 25 of 82) sorted by relevance

1234

/linux-5.10/drivers/tty/serial/8250/
D8250_ingenic.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010 Lars-Peter Clausen <lars@metafoo.de>
6 * Ingenic SoC UART support
27 int fifosize; member
47 return readl(port->membase + (offset << 2)); in early_in()
52 writel(value, port->membase + (offset << 2)); in early_out()
69 uart_console_write(&early_device->port, s, count, in ingenic_early_console_write()
83 prop = fdt_getprop(fdt, offset, "clock-frequency", NULL); in ingenic_early_console_setup_clock()
87 dev->port.uartclk = be32_to_cpup(prop); in ingenic_early_console_setup_clock()
93 struct uart_port *port = &dev->port; in ingenic_early_console_setup()
[all …]
D8250_of.c1 // SPDX-License-Identifier: GPL-2.0+
36 struct device_node *np = ofdev->dev.of_node; in of_platform_serial_setup()
37 struct uart_port *port = &up->port; in of_platform_serial_setup()
43 pm_runtime_enable(&ofdev->dev); in of_platform_serial_setup()
44 pm_runtime_get_sync(&ofdev->dev); in of_platform_serial_setup()
46 if (of_property_read_u32(np, "clock-frequency", &clk)) { in of_platform_serial_setup()
49 info->clk = devm_clk_get(&ofdev->dev, NULL); in of_platform_serial_setup()
50 if (IS_ERR(info->clk)) { in of_platform_serial_setup()
51 ret = PTR_ERR(info->clk); in of_platform_serial_setup()
52 if (ret != -EPROBE_DEFER) in of_platform_serial_setup()
[all …]
D8250_core.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Universal/legacy driver for 8250/16550-type serial ports
9 * Supports: ISA-compatible 8250/16550 ports
12 * userspace-configurable "phantom" ports
47 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
48 * is unsafe when used on edge-triggered interrupts.
62 * SERIAL_PORT_DFNS tells us about built-in ports that have no
103 * line has been de-asserted.
116 spin_lock(&i->lock); in serial8250_interrupt()
118 l = i->head; in serial8250_interrupt()
[all …]
D8250_dw.c1 // SPDX-License-Identifier: GPL-2.0+
10 * raised, the LCR needs to be rewritten and the uart status register read.
35 #define DW_UART_USR 0x1f /* UART Status Register */
73 struct dw8250_data *d = to_dw8250_data(p->private_data); in dw8250_modify_msr()
77 value |= d->msr_mask_on; in dw8250_modify_msr()
78 value &= ~d->msr_mask_off; in dw8250_modify_msr()
89 (void)p->serial_in(p, UART_RX); in dw8250_force_idle()
94 void __iomem *offset = p->membase + (UART_LCR << p->regshift); in dw8250_check_lcr()
98 while (tries--) { in dw8250_check_lcr()
99 unsigned int lcr = p->serial_in(p, UART_LCR); in dw8250_check_lcr()
[all …]
D8250_pxa.c1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/tty/serial/8250/8250_pxa.c -- driver for PXA on-board UARTS
38 serial8250_suspend_port(data->line); in serial_pxa_suspend()
47 serial8250_resume_port(data->line); in serial_pxa_resume()
57 { .compatible = "mrvl,pxa-uart", },
58 { .compatible = "mrvl,mmp-uart", },
63 /* Uart divisor latch write */
83 struct pxa8250_data *data = port->private_data; in serial_pxa_pm()
86 clk_prepare_enable(data->clk); in serial_pxa_pm()
88 clk_disable_unprepare(data->clk); in serial_pxa_pm()
[all …]
D8250_men_mcb.c1 // SPDX-License-Identifier: GPL-2.0
19 struct uart_8250_port uart; member
24 * The Z125 16550-compatible UART has no fixed base clock assigned
34 dev_info(&mdev->dev, "%s on board %s\n", in men_lookup_uartclk()
35 dev_name(&mdev->dev), in men_lookup_uartclk()
36 mdev->bus->name); in men_lookup_uartclk()
37 if (strncmp(mdev->bus->name, "F075", 4) == 0) in men_lookup_uartclk()
39 else if (strncmp(mdev->bus->name, "F216", 4) == 0) in men_lookup_uartclk()
41 else if (strncmp(mdev->bus->name, "G215", 4) == 0) in men_lookup_uartclk()
43 else if (strncmp(mdev->bus->name, "F210", 4) == 0) in men_lookup_uartclk()
[all …]
D8250_port.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Base port operations for 8250/16550-type serial ports
56 * Here we define the default xmit fifo size used for each type of UART.
255 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
256 * workaround of errata A-008006 which states that tx_loadsz should
268 .name = "Palmchip BK-3103",
311 /* Uart divisor latch read */
317 /* Uart divisor latch write */
326 /* Au1x00/RT288x UART hardware has a weird register layout */
335 -1, /* UART_SCR (unmapped) */
[all …]
D8250_bcm2835aux.c1 // SPDX-License-Identifier: GPL-2.0
3 * Serial port driver for BCM2835AUX UART
10 * The bcm2835aux is capable of RTS auto flow-control, but this driver doesn't
36 * struct bcm2835aux_data - driver private data of BCM2835 auxiliary UART
49 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX)) { in bcm2835aux_rs485_start_tx()
50 struct bcm2835aux_data *data = dev_get_drvdata(up->port.dev); in bcm2835aux_rs485_start_tx()
52 data->cntl &= ~BCM2835_AUX_UART_CNTL_RXEN; in bcm2835aux_rs485_start_tx()
53 serial_out(up, BCM2835_AUX_UART_CNTL, data->cntl); in bcm2835aux_rs485_start_tx()
58 * flags besides RTS. So no need for a read-modify-write. in bcm2835aux_rs485_start_tx()
60 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND) in bcm2835aux_rs485_start_tx()
[all …]
D8250_dwlib.c1 // SPDX-License-Identifier: GPL-2.0+
16 #define DW_UART_UCV 0xf8 /* UART Component Version */
37 if (p->iotype == UPIO_MEM32BE) in dw8250_readl_ext()
38 return ioread32be(p->membase + offset); in dw8250_readl_ext()
39 return readl(p->membase + offset); in dw8250_readl_ext()
44 if (p->iotype == UPIO_MEM32BE) in dw8250_writel_ext()
45 iowrite32be(reg, p->membase + offset); in dw8250_writel_ext()
47 writel(reg, p->membase + offset); in dw8250_writel_ext()
64 struct dw8250_port_data *d = p->private_data; in dw8250_get_divisor()
66 quot = p->uartclk / base_baud; in dw8250_get_divisor()
[all …]
/linux-5.10/Documentation/devicetree/bindings/serial/
Dsirf-uart.txt4 - compatible : Should be "sirf,prima2-uart", "sirf, prima2-usp-uart",
5 "sirf,atlas7-uart" or "sirf,atlas7-usp-uart".
6 - reg : Offset and length of the register set for the device
7 - interrupts : Should contain uart interrupt
8 - fifosize : Should define hardware rx/tx fifo size
9 - clocks : Should contain uart clock number
12 - uart-has-rtscts: we have hardware flow controller pins in hardware
13 - rts-gpios: RTS pin for USP-based UART if uart-has-rtscts is true
14 - cts-gpios: CTS pin for USP-based UART if uart-has-rtscts is true
18 uart0: uart@b0050000 {
[all …]
Dsamsung_uart.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S3C, S5P and Exynos SoC UART Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
14 Each Samsung UART should have an alias correctly numbered in the "aliases"
15 node, according to serialN format, where N is the port number (non-negative
21 - enum:
22 - samsung,s3c2410-uart
[all …]
/linux-5.10/drivers/tty/serial/
Dsirfsoc_uart.h1 /* SPDX-License-Identifier: GPL-2.0+ */
16 /* hardware uart specific */
19 /* uart - usp common */
112 full_bit = ilog2(port->fifosize); in uart_usp_ff_full_mask()
120 empty_bit = ilog2(port->fifosize) + 1; in uart_usp_ff_empty_mask()
186 .port_name = "sirfsoc-uart",
260 /* uart io ctrl */
287 /* UART FIFO Register */
330 /* USP-UART Common */
337 #define SIRFUART_FIFO_THD(port) (port->fifosize >> 1)
[all …]
Dsamsung_tty.c1 // SPDX-License-Identifier: GPL-2.0
5 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
12 * UERSTAT register in the UART blocks, and keeps marking some of the
21 * BJD, 04-Nov-2004
25 #include <linux/dma-mapping.h>
45 /* UART name and device definitions */
62 unsigned int fifosize; member
74 /* uart port features */
82 unsigned int fifosize[CONFIG_SERIAL_SAMSUNG_UARTS]; member
153 #define portaddr(port, reg) ((port)->membase + (reg))
[all …]
Dsccnxp.c1 // SPDX-License-Identifier: GPL-2.0+
24 #include <linux/platform_data/serial-sccnxp.h>
27 #define SCCNXP_NAME "uart-sccnxp"
93 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
94 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
106 unsigned int fifosize; member
112 struct uart_driver uart; member
142 .fifosize = 3,
153 .fifosize = 3,
164 .fifosize = 3,
[all …]
Dapbuart.c1 // SPDX-License-Identifier: GPL-2.0
10 * Copyright (C) 2008 Gilead Kutnick <kutnickg@zin-tech.com>
74 unsigned int max_chars = port->fifosize; in apbuart_rx_chars()
78 while (UART_RX_DATA(status) && (max_chars--)) { in apbuart_rx_chars()
83 port->icount.rx++; in apbuart_rx_chars()
91 port->icount.brk++; in apbuart_rx_chars()
95 port->icount.parity++; in apbuart_rx_chars()
97 port->icount.frame++; in apbuart_rx_chars()
100 port->icount.overrun++; in apbuart_rx_chars()
102 rsr &= port->read_status_mask; in apbuart_rx_chars()
[all …]
Dmsm_serial.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/dma-mapping.h>
171 struct uart_port uart; member
183 #define UART_TO_MSM(uart_port) container_of(uart_port, struct msm_port, uart)
188 writel_relaxed(val, port->membase + off); in msm_write()
194 return readl_relaxed(port->membase + off); in msm_read()
206 port->uartclk = 1843200; in msm_serial_set_mnd_regs_tcxo()
218 port->uartclk = 1843200; in msm_serial_set_mnd_regs_tcxoby4()
229 if (msm_port->is_uartdm) in msm_serial_set_mnd_regs()
232 if (port->uartclk == 19200000) in msm_serial_set_mnd_regs()
[all …]
Dbcm63xx_uart.c1 // SPDX-License-Identifier: GPL-2.0
7 * Serial driver for BCM63xx integrated UART.
37 * - rx fifo full
38 * - rx fifo above threshold
39 * - rx fifo not empty for too long
53 * - tx fifo empty
54 * - tx fifo below threshold
71 * handy uart register accessor
76 return __raw_readl(port->membase + offset); in bcm_uart_readl()
82 __raw_writel(value, port->membase + offset); in bcm_uart_writel()
[all …]
Dpch_uart.c1 // SPDX-License-Identifier: GPL-2.0
36 /* Set the max number of UART port
248 * struct pch_uart_driver_data - private data structure for UART-DMA
249 * @port_type: The type of UART port
250 * @line_no: UART port line number (0, 1, 2...)
303 struct eg20t_port *priv = file->private_data; in port_show_regs()
313 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs()
314 "PCH EG20T port[%d] regs:\n", priv->port.line); in port_show_regs()
316 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs()
318 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs()
[all …]
Damba-pl011.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (C) 2010 ST-Ericsson SA
11 * This is a generic driver for ARM AMBA-type serial ports. They
12 * have a lot of 16550-like features, but are not register compatible.
34 #include <linux/dma-mapping.h>
45 #include "amba-pl011.h"
264 unsigned int fifosize; /* vendor-specific */ member
266 unsigned int fixed_baud; /* vendor-set fixed baud rate */
281 return uap->reg_offset[reg]; in pl011_reg_to_offset()
287 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); in pl011_read()
[all …]
Dsirfsoc_uart.c1 // SPDX-License-Identifier: GPL-2.0+
24 #include <linux/dma-direction.h>
25 #include <linux/dma-mapping.h>
70 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; in sirfsoc_uart_tx_empty()
71 struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status; in sirfsoc_uart_tx_empty()
72 reg = rd_regl(port, ureg->sirfsoc_tx_fifo_status); in sirfsoc_uart_tx_empty()
73 return (reg & ufifo_st->ff_empty(port)) ? TIOCSER_TEMT : 0; in sirfsoc_uart_tx_empty()
79 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; in sirfsoc_uart_get_mctrl()
80 if (!sirfport->hw_flow_ctrl || !sirfport->ms_enabled) in sirfsoc_uart_get_mctrl()
82 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) { in sirfsoc_uart_get_mctrl()
[all …]
D21285.c1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for the serial port on the 21285 StrongArm-110 core logic chip.
19 #include <asm/mach-types.h>
42 static const char serial21285_name[] = "Footbridge UART";
46 * this, use bits of the private_data pointer of the uart port structure.
53 unsigned long *private_data = (unsigned long *)&port->private_data; in is_enabled()
62 unsigned long *private_data = (unsigned long *)&port->private_data; in enable()
69 unsigned long *private_data = (unsigned long *)&port->private_data; in disable()
84 * BAUD_BASE / baud - 1
88 * int(BAUD_BASE / baud - 0.5) ->
[all …]
/linux-5.10/arch/arm/boot/dts/
Dprima2.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #address-cells = <1>;
11 #size-cells = <1>;
12 interrupt-parent = <&intc>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a9";
22 d-cache-line-size = <32>;
23 i-cache-line-size = <32>;
24 d-cache-size = <32768>;
[all …]
Datlas6.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #address-cells = <1>;
11 #size-cells = <1>;
12 interrupt-parent = <&intc>;
15 #address-cells = <1>;
16 #size-cells = <0>;
20 d-cache-line-size = <32>;
21 i-cache-line-size = <32>;
22 d-cache-size = <32768>;
23 i-cache-size = <32768>;
[all …]
Datlas7.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #address-cells = <1>;
11 #size-cells = <1>;
12 interrupt-parent = <&gic>;
28 #address-cells = <1>;
29 #size-cells = <0>;
33 compatible = "arm,cortex-a7";
38 compatible = "arm,cortex-a7";
45 compatible = "fixed-clock";
46 #clock-cells = <0>;
[all …]
/linux-5.10/Documentation/devicetree/bindings/clock/
Dcsr,atlas7-car.txt4 - compatible: Should be "sirf,atlas7-car"
5 - reg: Address and length of the register set
6 - #clock-cells: Should be <1>
7 - #reset-cells: Should be <1>
11 The ID list atlas7_clks defined in drivers/clk/sirf/clk-atlas7.c
15 The ID list atlas7_reset_unit defined in drivers/clk/sirf/clk-atlas7.c
19 car: clock-controller@18620000 {
20 compatible = "sirf,atlas7-car";
22 #clock-cells = <1>;
23 #reset-cells = <1>;
[all …]

1234