Lines Matching +full:uart +full:- +full:fifosize
1 // SPDX-License-Identifier: GPL-2.0+
16 #define DW_UART_UCV 0xf8 /* UART Component Version */
37 if (p->iotype == UPIO_MEM32BE) in dw8250_readl_ext()
38 return ioread32be(p->membase + offset); in dw8250_readl_ext()
39 return readl(p->membase + offset); in dw8250_readl_ext()
44 if (p->iotype == UPIO_MEM32BE) in dw8250_writel_ext()
45 iowrite32be(reg, p->membase + offset); in dw8250_writel_ext()
47 writel(reg, p->membase + offset); in dw8250_writel_ext()
64 struct dw8250_port_data *d = p->private_data; in dw8250_get_divisor()
66 quot = p->uartclk / base_baud; in dw8250_get_divisor()
67 rem = p->uartclk % base_baud; in dw8250_get_divisor()
68 *frac = DIV_ROUND_CLOSEST(rem << d->dlf_size, base_baud); in dw8250_get_divisor()
93 dev_dbg(p->dev, "Designware UART version %c.%c%c\n", in dw8250_setup_port()
101 struct dw8250_port_data *d = p->private_data; in dw8250_setup_port()
103 d->dlf_size = fls(reg); in dw8250_setup_port()
104 p->get_divisor = dw8250_get_divisor; in dw8250_setup_port()
105 p->set_divisor = dw8250_set_divisor; in dw8250_setup_port()
114 p->type = PORT_16550A; in dw8250_setup_port()
115 p->flags |= UPF_FIXED_TYPE; in dw8250_setup_port()
116 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg); in dw8250_setup_port()
117 up->capabilities = UART_CAP_FIFO; in dw8250_setup_port()
121 up->capabilities |= UART_CAP_AFE; in dw8250_setup_port()
124 up->capabilities |= UART_CAP_IRDA; in dw8250_setup_port()