1 // SPDX-License-Identifier: GPL-2.0
3  * Serial port driver for BCM2835AUX UART
10  * The bcm2835aux is capable of RTS auto flow-control, but this driver doesn't
36  * struct bcm2835aux_data - driver private data of BCM2835 auxiliary UART
49 	if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX)) {  in bcm2835aux_rs485_start_tx()
50 		struct bcm2835aux_data *data = dev_get_drvdata(up->port.dev);  in bcm2835aux_rs485_start_tx()
52 		data->cntl &= ~BCM2835_AUX_UART_CNTL_RXEN;  in bcm2835aux_rs485_start_tx()
53 		serial_out(up, BCM2835_AUX_UART_CNTL, data->cntl);  in bcm2835aux_rs485_start_tx()
58 	 * flags besides RTS.  So no need for a read-modify-write.  in bcm2835aux_rs485_start_tx()
60 	if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)  in bcm2835aux_rs485_start_tx()
68 	if (up->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)  in bcm2835aux_rs485_stop_tx()
73 	if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX)) {  in bcm2835aux_rs485_stop_tx()
74 		struct bcm2835aux_data *data = dev_get_drvdata(up->port.dev);  in bcm2835aux_rs485_stop_tx()
76 		data->cntl |= BCM2835_AUX_UART_CNTL_RXEN;  in bcm2835aux_rs485_stop_tx()
77 		serial_out(up, BCM2835_AUX_UART_CNTL, data->cntl);  in bcm2835aux_rs485_stop_tx()
89 	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);  in bcm2835aux_serial_probe()
91 		return -ENOMEM;  in bcm2835aux_serial_probe()
95 	up.port.dev = &pdev->dev;  in bcm2835aux_serial_probe()
99 	up.port.fifosize = 8;  in bcm2835aux_serial_probe()
106 	/* initialize cached copy with power-on reset value */  in bcm2835aux_serial_probe()
107 	data->cntl = BCM2835_AUX_UART_CNTL_RXEN | BCM2835_AUX_UART_CNTL_TXEN;  in bcm2835aux_serial_probe()
111 	/* get the clock - this also enables the HW */  in bcm2835aux_serial_probe()
112 	data->clk = devm_clk_get(&pdev->dev, NULL);  in bcm2835aux_serial_probe()
113 	if (IS_ERR(data->clk))  in bcm2835aux_serial_probe()
114 		return dev_err_probe(&pdev->dev, PTR_ERR(data->clk), "could not get clk\n");  in bcm2835aux_serial_probe()
125 		dev_err(&pdev->dev, "memory resource not found");  in bcm2835aux_serial_probe()
126 		return -EINVAL;  in bcm2835aux_serial_probe()
128 	up.port.mapbase = res->start;  in bcm2835aux_serial_probe()
132 	ret = of_alias_get_id(pdev->dev.of_node, "serial");  in bcm2835aux_serial_probe()
137 	ret = clk_prepare_enable(data->clk);  in bcm2835aux_serial_probe()
139 		dev_err(&pdev->dev, "unable to enable uart clock - %d\n",  in bcm2835aux_serial_probe()
144 	/* the HW-clock divider for bcm2835aux is 8,  in bcm2835aux_serial_probe()
149 	up.port.uartclk = clk_get_rate(data->clk) * 2;  in bcm2835aux_serial_probe()
154 		dev_err_probe(&pdev->dev, ret, "unable to register 8250 port\n");  in bcm2835aux_serial_probe()
157 	data->line = ret;  in bcm2835aux_serial_probe()
162 	clk_disable_unprepare(data->clk);  in bcm2835aux_serial_probe()
170 	serial8250_unregister_port(data->line);  in bcm2835aux_serial_remove()
171 	clk_disable_unprepare(data->clk);  in bcm2835aux_serial_remove()
177 	{ .compatible = "brcm,bcm2835-aux-uart" },
184 		.name = "bcm2835-aux-uart",
197 	if (!device->port.membase)  in early_bcm2835aux_setup()
198 		return -ENODEV;  in early_bcm2835aux_setup()
200 	device->port.iotype = UPIO_MEM32;  in early_bcm2835aux_setup()
201 	device->port.regshift = 2;  in early_bcm2835aux_setup()
206 OF_EARLYCON_DECLARE(bcm2835aux, "brcm,bcm2835-aux-uart",
210 MODULE_DESCRIPTION("BCM2835 auxiliar UART driver");