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/linux-6.15/Documentation/devicetree/bindings/net/
Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
22 SGMII The DP83869HM supports Media Conversion in Managed mode. In this mode,
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Dadi,adin.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandru Tachici <alexandru.tachici@analog.com>
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
21 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
28 RGMII TX Clock Delay used only when PHY operates in RGMII mode with
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Dti,dp83867.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Andrew Davis <afd@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
34 nvmem-cells:
40 nvmem-cell-names:
42 - const: io_impedance_ctrl
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Dmotorcomm,yt8xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Sae <frank.sae@motor-comm.com>
13 - $ref: ethernet-phy.yaml#
18 - ethernet-phy-id4f51.e91a
19 - ethernet-phy-id4f51.e91b
21 rx-internal-delay-ps:
23 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
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Dqcom,qca807x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christian Marangi <ansuelsmth@gmail.com>
11 - Robert Marko <robert.marko@sartura.hr>
15 IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and
16 1000BASE-T PHY-s.
21 Both models have a combo port that supports 1000BASE-X and
22 100BASE-FX fiber.
25 output only pins that natively drive LED-s for up to 2 attached
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Dsff,sfp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Small Form Factor (SFF) Committee Small Form-factor Pluggable (SFP)
11 - Russell King <linux@armlinux.org.uk>
16 - sff,sfp # for SFP modules
17 - sff,sff # for soldered down SFF modules
19 i2c-bus:
24 maximum-power-milliwatt:
29 allowable by a module in the slot, in milli-Watts. Presently, modules can
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/linux-6.15/Documentation/devicetree/bindings/net/can/
Dnxp,sja1000.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wolfgang Grandegger <wg@grandegger.com>
15 - enum:
16 - nxp,sja1000
17 - technologic,sja1000
18 - items:
19 - enum:
20 - renesas,r9a06g032-sja1000 # RZ/N1D
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/linux-6.15/drivers/net/hamradio/
Dz8530.h1 /* SPDX-License-Identifier: GPL-2.0 */
34 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
40 #define TxINT_ENAB 0x2 /* Tx Int Enable */
58 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
60 #define ENT_HM 0x10 /* Enter Hunt Mode */
79 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
80 #define EXTSYNC 0x30 /* External Sync Mode */
82 #define X1CLK 0x0 /* x1 clock mode */
83 #define X16CLK 0x40 /* x16 clock mode */
84 #define X32CLK 0x80 /* x32 clock mode */
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/linux-6.15/arch/arm64/boot/dts/microchip/
Dsparx5_pcb134_board.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 gpio-restart {
11 compatible = "gpio-restart";
16 i2c0_imux: i2c-mux-0 {
17 compatible = "i2c-mux-pinctrl";
18 #address-cells = <1>;
19 #size-cells = <0>;
20 i2c-parent = <&i2c0>;
23 i2c0_emux: i2c-mux-1 {
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Dsparx5_pcb135_board.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 gpio-restart {
11 compatible = "gpio-restart";
16 i2c0_imux: i2c-mux {
17 compatible = "i2c-mux-pinctrl";
18 #address-cells = <1>;
19 #size-cells = <0>;
20 i2c-parent = <&i2c0>;
24 compatible = "gpio-leds";
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/linux-6.15/drivers/tty/serial/
Dzs.h1 /* SPDX-License-Identifier: GPL-2.0 */
29 int tx_stopped; /* Output is suspended. */
38 * Per-SCC state for locking and the interrupt handler.
53 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
87 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
90 /* Write Register 1 (Tx/Rx/Ext Int Enable and WAIT/DMA Commands) */
92 #define TxINT_ENAB 0x2 /* Tx Int Enable */
110 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
112 #define ENT_HM 0x10 /* Enter Hunt Mode */
132 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
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Dip22zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
66 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
72 #define TxINT_ENAB 0x2 /* Tx Int Enable */
91 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
93 #define ENT_HM 0x10 /* Enter Hunt Mode */
113 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
114 #define EXTSYNC 0x30 /* External Sync Mode */
116 #define X1CLK 0x0 /* x1 clock mode */
117 #define X16CLK 0x40 /* x16 clock mode */
[all …]
Dsunzilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
58 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
64 #define TxINT_ENAB 0x2 /* Tx Int Enable */
83 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
85 #define ENT_HM 0x10 /* Enter Hunt Mode */
105 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
106 #define EXTSYNC 0x30 /* External Sync Mode */
108 #define X1CLK 0x0 /* x1 clock mode */
109 #define X16CLK 0x40 /* x16 clock mode */
[all …]
Dpmac_zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 * of "escc" node (ie. ch-a or ch-b)
64 if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A) in pmz_get_port_A()
66 return uap->mate; in pmz_get_port_A()
78 writeb(reg, port->control_reg); in read_zsreg()
79 return readb(port->control_reg); in read_zsreg()
85 writeb(reg, port->control_reg); in write_zsreg()
86 writeb(value, port->control_reg); in write_zsreg()
91 return readb(port->data_reg); in read_zsdata()
96 writeb(data, port->data_reg); in write_zsdata()
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/linux-6.15/tools/spi/
Dspidev_test.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Cross-compile with cross-gcc -I/path/to/cross-kernel/include
39 static uint32_t mode; variable
72 while (length-- > 0) { in hex_dump()
92 * Unescape - process hexadecimal escape character
93 * converts shell input "\x23" -> 0x23
119 static void transfer(int fd, uint8_t const *tx, uint8_t const *rx, size_t len) in transfer() argument
124 .tx_buf = (unsigned long)tx, in transfer()
133 if (mode & SPI_TX_OCTAL) in transfer()
135 else if (mode & SPI_TX_QUAD) in transfer()
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/linux-6.15/Documentation/networking/devlink/
Dmlx5.rst1 .. SPDX-License-Identifier: GPL-2.0
13 .. list-table:: Generic parameters implemented
15 * - Name
16 - Mode
17 - Validation
18 * - ``enable_roce``
19 - driverinit
20 - Type: Boolean
26 * - ``io_eq_size``
27 - driverinit
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/linux-6.15/tools/testing/vsock/
DREADME2 -------------------
3 These tests exercise net/vmw_vsock/ host<->guest sockets for VMware, KVM, and
4 Hyper-V.
8 * vsock_test - core AF_VSOCK socket functionality
9 * vsock_diag_test - vsock_diag.ko module for listing open sockets
22 (host)# $TEST_BINARY --mode=server \
23 --control-port=1234 \
24 --peer-cid=3
25 (guest)# $TEST_BINARY --mode=client \
26 --control-host=$HOST_IP \
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/linux-6.15/drivers/net/ethernet/sun/
Dsungem.h1 /* SPDX-License-Identifier: GPL-2.0 */
30 #define GREG_CFG_TXDMALIM 0x0000003e /* TX DMA grant limit */
39 * This auto-clearing does not occur when the alias at GREG_STAT2
45 #define GREG_STAT_TXINTME 0x00000001 /* TX INTME frame transferred */
46 #define GREG_STAT_TXALL 0x00000002 /* All TX frames transferred */
47 #define GREG_STAT_TXDONE 0x00000004 /* One TX frame transferred */
52 #define GREG_STAT_TXMAC 0x00004000 /* TX MAC signalled interrupt */
69 * signalled to the cpu. GREG_IACK can be used to clear specific top-level
96 * This register is used to perform a global reset of the RX and TX portions
97 * of the GEM asic. Setting the RX or TX reset bit will start the reset.
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/linux-6.15/arch/m68k/include/asm/
Dmcfuart.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * mcfuart.h -- ColdFire internal UART support defines.
7 * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com)
29 #define MCFUART_UMR 0x00 /* Mode register (r/w) */
52 #define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */
53 #define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */
57 * Define bit flags in Mode Register 1 (MR1).
62 #define MCFUART_MR1_RXERRBLOCK 0x20 /* RX block error mode */
63 #define MCFUART_MR1_RXERRCHAR 0x00 /* RX char error mode */
77 * Define bit flags in Mode Register 2 (MR2).
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/linux-6.15/sound/drivers/mpu401/
Dmpu401_uart.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Routines for control of MPU-401 in UART mode
6 * MPU-401 supports UART mode which is not capable generate transmit
7 * interrupts thus output is done via polling. Without interrupt,
10 * 13-03-2003:
12 * are port and mmio. For other kind of I/O, set mpu->read and
13 * mpu->write to your own I/O functions.
28 MODULE_DESCRIPTION("Routines for control of MPU-401 in UART mode");
39 (!(mpu->read(mpu, MPU401C(mpu)) & MPU401_RX_EMPTY))
41 (!(mpu->read(mpu, MPU401C(mpu)) & MPU401_TX_FULL))
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/linux-6.15/samples/pktgen/
Dparameters.sh2 # SPDX-License-Identifier: GPL-2.0
8 echo "Usage: $0 [-vx] -i ethX"
9 echo " -i : (\$DEV) output interface/device (required)"
10 echo " -s : (\$PKT_SIZE) packet size"
11 echo " -d : (\$DEST_IP) destination IP. CIDR (e.g. 198.18.0.0/15) is also allowed"
12 echo " -m : (\$DST_MAC) destination MAC-addr"
13 echo " -p : (\$DST_PORT) destination PORT range (e.g. 433-444) is also allowed"
14 echo " -k : (\$UDP_CSUM) enable UDP tx checksum"
15 echo " -t : (\$THREADS) threads to start"
16 echo " -f : (\$F_THREAD) index of first thread (zero indexed CPU number)"
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/linux-6.15/Documentation/userspace-api/media/cec/
Dcec-pin-error-inj.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
9 has low-level support for the CEC bus. Most hardware today will have
10 high-level CEC support where the hardware deals with driving the CEC bus,
19 Currently only the cec-gpio driver (when the CEC line is directly
20 connected to a pull-up GPIO line) and the AllWinner A10/A20 drm driver
25 now an ``error-inj`` file.
32 With ``cat error-inj`` you can see both the possible commands and the current
35 $ cat /sys/kernel/debug/cec/cec0/error-inj
37 # clear clear all rx and tx error injections
38 # rx-clear clear all rx error injections
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/linux-6.15/Documentation/networking/device_drivers/ethernet/3com/
Dvortex.rst1 .. SPDX-License-Identifier: GPL-2.0
20 - Andrew Morton
21 - Netdev mailing list <netdev@vger.kernel.org>
22 - Linux kernel mailing list <linux-kernel@vger.kernel.org>
28 Since kernel 2.3.99-pre6, this driver incorporates the support for the
29 3c575-series Cardbus cards which used to be handled by 3c575_cb.c.
33 - 3c590 Vortex 10Mbps
34 - 3c592 EISA 10Mbps Demon/Vortex
35 - 3c597 EISA Fast Demon/Vortex
36 - 3c595 Vortex 100baseTx
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/linux-6.15/Documentation/devicetree/bindings/usb/
Dsnps,dwc3-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/snps,dwc3-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
14 vendor-specific implementation or as a standalone component.
17 - $ref: usb-drd.yaml#
18 - if:
24 - dr_mode
28 $ref: usb-xhci.yaml#
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/linux-6.15/drivers/net/phy/
Ddp83867.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/nvmem-consumer.h>
19 #include <dt-bindings/net/ti-dp83867.h>
167 #define DP83867_LED_FN_LINK_RX_TX 0xb /* Link established, blink for rx or tx activity */
212 struct net_device *ndev = phydev->attached_dev; in dp83867_set_wol()
219 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST | in dp83867_set_wol()
224 if (wol->wolopts & WAKE_MAGIC) { in dp83867_set_wol()
225 mac = (const u8 *)ndev->dev_addr; in dp83867_set_wol()
228 return -EINVAL; in dp83867_set_wol()
242 if (wol->wolopts & WAKE_MAGICSECURE) { in dp83867_set_wol()
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