1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/usb/snps,dwc3-common.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Synopsys DesignWare USB3 Controller common properties 8 9maintainers: 10 - Felipe Balbi <balbi@kernel.org> 11 12description: 13 Defines the properties of the DWC3 core as being embedded in either an 14 vendor-specific implementation or as a standalone component. 15 16allOf: 17 - $ref: usb-drd.yaml# 18 - if: 19 properties: 20 dr_mode: 21 const: peripheral 22 23 required: 24 - dr_mode 25 then: 26 $ref: usb.yaml# 27 else: 28 $ref: usb-xhci.yaml# 29 30properties: 31 extcon: 32 maxItems: 1 33 deprecated: true 34 35 usb-phy: 36 minItems: 1 37 items: 38 - description: USB2/HS PHY 39 - description: USB3/SS PHY 40 41 phys: 42 minItems: 1 43 maxItems: 19 44 45 phy-names: 46 minItems: 1 47 maxItems: 19 48 oneOf: 49 - items: 50 enum: [ usb2-phy, usb3-phy ] 51 - items: 52 pattern: "^usb(2-([0-9]|1[0-4])|3-[0-3])$" 53 54 snps,usb2-lpm-disable: 55 description: Indicate if we don't want to enable USB2 HW LPM for host 56 mode. 57 type: boolean 58 59 snps,usb3_lpm_capable: 60 description: Determines if platform is USB3 LPM capable 61 type: boolean 62 63 snps,usb2-gadget-lpm-disable: 64 description: Indicate if we don't want to enable USB2 HW LPM for gadget 65 mode. 66 type: boolean 67 68 snps,reserved-endpoints: 69 description: 70 Reserve endpoints for other needs, e.g, for tracing control and output. 71 When set, the driver will avoid using them for the regular USB transfers. 72 $ref: /schemas/types.yaml#/definitions/uint8-array 73 minItems: 1 74 maxItems: 30 75 items: 76 minimum: 2 77 maximum: 31 78 79 snps,dis-start-transfer-quirk: 80 description: 81 When set, disable isoc START TRANSFER command failure SW work-around 82 for DWC_usb31 version 1.70a-ea06 and prior. 83 type: boolean 84 85 snps,disable_scramble_quirk: 86 description: 87 True when SW should disable data scrambling. Only really useful for FPGA 88 builds. 89 type: boolean 90 91 snps,has-lpm-erratum: 92 description: True when DWC3 was configured with LPM Erratum enabled 93 type: boolean 94 95 snps,lpm-nyet-threshold: 96 description: LPM NYET threshold 97 $ref: /schemas/types.yaml#/definitions/uint8 98 99 snps,u2exit_lfps_quirk: 100 description: Set if we want to enable u2exit lfps quirk 101 type: boolean 102 103 snps,u2ss_inp3_quirk: 104 description: Set if we enable P3 OK for U2/SS Inactive quirk 105 type: boolean 106 107 snps,req_p1p2p3_quirk: 108 description: 109 When set, the core will always request for P1/P2/P3 transition sequence. 110 type: boolean 111 112 snps,del_p1p2p3_quirk: 113 description: 114 When set core will delay P1/P2/P3 until a certain amount of 8B10B errors 115 occur. 116 type: boolean 117 118 snps,del_phy_power_chg_quirk: 119 description: When set core will delay PHY power change from P0 to P1/P2/P3. 120 type: boolean 121 122 snps,lfps_filter_quirk: 123 description: When set core will filter LFPS reception. 124 type: boolean 125 126 snps,rx_detect_poll_quirk: 127 description: 128 when set core will disable a 400us delay to start Polling LFPS after 129 RX.Detect. 130 type: boolean 131 132 snps,tx_de_emphasis_quirk: 133 description: When set core will set Tx de-emphasis value 134 type: boolean 135 136 snps,tx_de_emphasis: 137 description: 138 The value driven to the PHY is controlled by the LTSSM during USB3 139 Compliance mode. 140 $ref: /schemas/types.yaml#/definitions/uint8 141 enum: 142 - 0 # -6dB de-emphasis 143 - 1 # -3.5dB de-emphasis 144 - 2 # No de-emphasis 145 146 snps,dis_u3_susphy_quirk: 147 description: When set core will disable USB3 suspend phy 148 type: boolean 149 150 snps,dis_u2_susphy_quirk: 151 description: When set core will disable USB2 suspend phy 152 type: boolean 153 154 snps,dis_enblslpm_quirk: 155 description: 156 When set clears the enblslpm in GUSB2PHYCFG, disabling the suspend signal 157 to the PHY. 158 type: boolean 159 160 snps,dis-u1-entry-quirk: 161 description: Set if link entering into U1 needs to be disabled 162 type: boolean 163 164 snps,dis-u2-entry-quirk: 165 description: Set if link entering into U2 needs to be disabled 166 type: boolean 167 168 snps,dis_rxdet_inp3_quirk: 169 description: 170 When set core will disable receiver detection in PHY P3 power state. 171 type: boolean 172 173 snps,dis-u2-freeclk-exists-quirk: 174 description: 175 When set, clear the u2_freeclk_exists in GUSB2PHYCFG, specify that USB2 176 PHY doesn't provide a free-running PHY clock. 177 type: boolean 178 179 snps,dis-del-phy-power-chg-quirk: 180 description: 181 When set core will change PHY power from P0 to P1/P2/P3 without delay. 182 type: boolean 183 184 snps,dis-tx-ipgap-linecheck-quirk: 185 description: When set, disable u2mac linestate check during HS transmit 186 type: boolean 187 188 snps,parkmode-disable-ss-quirk: 189 description: 190 When set, all SuperSpeed bus instances in park mode are disabled. 191 type: boolean 192 193 snps,parkmode-disable-hs-quirk: 194 description: 195 When set, all HighSpeed bus instances in park mode are disabled. 196 type: boolean 197 198 snps,dis_metastability_quirk: 199 description: 200 When set, disable metastability workaround. CAUTION! Use only if you are 201 absolutely sure of it. 202 type: boolean 203 204 snps,dis-split-quirk: 205 description: 206 When set, change the way URBs are handled by the driver. Needed to 207 avoid -EPROTO errors with usbhid on some devices (Hikey 970). 208 type: boolean 209 210 snps,gfladj-refclk-lpm-sel-quirk: 211 description: 212 When set, run the SOF/ITP counter based on ref_clk. 213 type: boolean 214 215 snps,resume-hs-terminations: 216 description: 217 Fix the issue of HS terminations CRC error on resume by enabling this 218 quirk. When set, all the termsel, xcvrsel, opmode becomes 0 during end 219 of resume. This option is to support certain legacy ULPI PHYs. 220 type: boolean 221 222 snps,ulpi-ext-vbus-drv: 223 description: 224 Some ULPI USB PHY does not support internal VBUS supply, and driving 225 the CPEN pin, requires the configuration of the ulpi DRVVBUSEXTERNAL 226 bit. When set, the xhci host will configure the USB2 PHY drives VBUS 227 with an external supply. 228 type: boolean 229 230 snps,is-utmi-l1-suspend: 231 description: 232 True when DWC3 asserts output signal utmi_l1_suspend_n, false when 233 asserts utmi_sleep_n. 234 type: boolean 235 236 snps,hird-threshold: 237 description: HIRD threshold 238 $ref: /schemas/types.yaml#/definitions/uint8 239 240 snps,hsphy_interface: 241 description: 242 High-Speed PHY interface selection between UTMI+ and ULPI when the 243 DWC_USB3_HSPHY_INTERFACE has value 3. 244 $ref: /schemas/types.yaml#/definitions/string 245 enum: [utmi, ulpi] 246 247 snps,quirk-frame-length-adjustment: 248 description: 249 Value for GFLADJ_30MHZ field of GFLADJ register for post-silicon frame 250 length adjustment when the fladj_30mhz_sdbnd signal is invalid or 251 incorrect. 252 $ref: /schemas/types.yaml#/definitions/uint32 253 minimum: 0 254 maximum: 0x3f 255 256 snps,ref-clock-period-ns: 257 description: 258 Value for REFCLKPER field of GUCTL register for reference clock period in 259 nanoseconds, when the hardware set default does not match the actual 260 clock. 261 262 This binding is deprecated. Instead, provide an appropriate reference clock. 263 minimum: 8 264 maximum: 62 265 deprecated: true 266 267 snps,rx-thr-num-pkt: 268 description: 269 USB RX packet threshold count. In host mode, this field specifies 270 the space that must be available in the RX FIFO before the core can 271 start the corresponding USB RX transaction (burst). 272 In device mode, this field specifies the space that must be 273 available in the RX FIFO before the core can send ERDY for a 274 flow-controlled endpoint. It is only used for SuperSpeed. 275 The valid values for this field are from 1 to 15. (DWC3 SuperSpeed 276 USB 3.0 Controller Databook) 277 $ref: /schemas/types.yaml#/definitions/uint8 278 minimum: 1 279 maximum: 15 280 281 snps,rx-max-burst: 282 description: 283 Max USB RX burst size. In host mode, this field specifies the 284 Maximum Bulk IN burst the DWC_usb3 core can perform. When the system 285 bus is slower than the USB, RX FIFO can overrun during a long burst. 286 You can program a smaller value to this field to limit the RX burst 287 size that the core can perform. It only applies to SS Bulk, 288 Isochronous, and Interrupt IN endpoints in the host mode. 289 In device mode, this field specifies the NUMP value that is sent in 290 ERDY for an OUT endpoint. 291 The valid values for this field are from 1 to 16. (DWC3 SuperSpeed 292 USB 3.0 Controller Databook) 293 $ref: /schemas/types.yaml#/definitions/uint8 294 minimum: 1 295 maximum: 16 296 297 snps,tx-thr-num-pkt: 298 description: 299 USB TX packet threshold count. This field specifies the number of 300 packets that must be in the TXFIFO before the core can start 301 transmission for the corresponding USB transaction (burst). 302 This count is valid in both host and device modes. It is only used 303 for SuperSpeed operation. 304 Valid values are from 1 to 15. (DWC3 SuperSpeed USB 3.0 Controller 305 Databook) 306 $ref: /schemas/types.yaml#/definitions/uint8 307 minimum: 1 308 maximum: 15 309 310 snps,tx-max-burst: 311 description: 312 Max USB TX burst size. When the system bus is slower than the USB, 313 TX FIFO can underrun during a long burst. Program a smaller value 314 to this field to limit the TX burst size that the core can execute. 315 In Host mode, it only applies to SS Bulk, Isochronous, and Interrupt 316 OUT endpoints. This value is not used in device mode. 317 Valid values are from 1 to 16. (DWC3 SuperSpeed USB 3.0 Controller 318 Databook) 319 $ref: /schemas/types.yaml#/definitions/uint8 320 minimum: 1 321 maximum: 16 322 323 snps,rx-thr-num-pkt-prd: 324 description: 325 Periodic ESS RX packet threshold count (host mode only). Set this and 326 snps,rx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31 327 programming guide section 1.2.4) to enable periodic ESS RX threshold. 328 $ref: /schemas/types.yaml#/definitions/uint8 329 minimum: 1 330 maximum: 16 331 332 snps,rx-max-burst-prd: 333 description: 334 Max periodic ESS RX burst size (host mode only). Set this and 335 snps,rx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31 336 programming guide section 1.2.4) to enable periodic ESS RX threshold. 337 $ref: /schemas/types.yaml#/definitions/uint8 338 minimum: 1 339 maximum: 16 340 341 snps,tx-thr-num-pkt-prd: 342 description: 343 Periodic ESS TX packet threshold count (host mode only). Set this and 344 snps,tx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31 345 programming guide section 1.2.3) to enable periodic ESS TX threshold. 346 $ref: /schemas/types.yaml#/definitions/uint8 347 minimum: 1 348 maximum: 16 349 350 snps,tx-max-burst-prd: 351 description: 352 Max periodic ESS TX burst size (host mode only). Set this and 353 snps,tx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31 354 programming guide section 1.2.3) to enable periodic ESS TX threshold. 355 $ref: /schemas/types.yaml#/definitions/uint8 356 minimum: 1 357 maximum: 16 358 359 tx-fifo-resize: 360 description: Determines if the TX fifos can be dynamically resized depending 361 on the number of IN endpoints used and if bursting is supported. This 362 may help improve bandwidth on platforms with higher system latencies, as 363 increased fifo space allows for the controller to prefetch data into its 364 internal memory. 365 type: boolean 366 367 tx-fifo-max-num: 368 description: Specifies the max number of packets the txfifo resizing logic 369 can account for when higher endpoint bursting is used. (bMaxBurst > 6) The 370 higher the number, the more fifo space the txfifo resizing logic will 371 allocate for that endpoint. 372 $ref: /schemas/types.yaml#/definitions/uint8 373 minimum: 3 374 375 snps,incr-burst-type-adjustment: 376 description: 377 Value for INCR burst type of GSBUSCFG0 register, undefined length INCR 378 burst type enable and INCRx type. A single value means INCRX burst mode 379 enabled. If more than one value specified, undefined length INCR burst 380 type will be enabled with burst lengths utilized up to the maximum 381 of the values passed in this property. 382 $ref: /schemas/types.yaml#/definitions/uint32-array 383 minItems: 1 384 maxItems: 8 385 uniqueItems: true 386 items: 387 enum: [1, 4, 8, 16, 32, 64, 128, 256] 388 389 num-hc-interrupters: 390 maximum: 8 391 default: 1 392 393 port: 394 $ref: /schemas/graph.yaml#/properties/port 395 description: 396 This port is used with the 'usb-role-switch' property to connect the 397 dwc3 to type C connector. 398 399 ports: 400 $ref: /schemas/graph.yaml#/properties/ports 401 description: 402 Those ports should be used with any connector to the data bus of this 403 controller using the OF graph bindings specified if the "usb-role-switch" 404 property is used. 405 406 properties: 407 port@0: 408 $ref: /schemas/graph.yaml#/properties/port 409 description: High Speed (HS) data bus. 410 411 port@1: 412 $ref: /schemas/graph.yaml#/properties/port 413 description: Super Speed (SS) data bus. 414 415 wakeup-source: 416 $ref: /schemas/types.yaml#/definitions/flag 417 description: 418 Enable USB remote wakeup. 419 420required: 421 - compatible 422 - reg 423 424additionalProperties: true 425... 426 427