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Searched +full:spi +full:- +full:rx +full:- +full:bus +full:- +full:width (Results 1 – 25 of 35) sorted by relevance

12

/linux-3.3/arch/powerpc/boot/dts/
Dpdm360ng.dts4 * Copyright 2009 - 2010 DENX Software Engineering.
16 /dts-v1/;
21 #address-cells = <1>;
22 #size-cells = <1>;
23 interrupt-parent = <&ipic>;
30 #address-cells = <1>;
31 #size-cells = <0>;
36 d-cache-line-size = <0x20>; // 32 bytes
37 i-cache-line-size = <0x20>; // 32 bytes
38 d-cache-size = <0x8000>; // L1, 32K
[all …]
Dmpc836x_rdk.dts5 * Copyright 2007-2008 MontaVista Software, Inc.
15 /dts-v1/;
18 #address-cells = <1>;
19 #size-cells = <1>;
35 #address-cells = <1>;
36 #size-cells = <0>;
41 d-cache-line-size = <32>;
42 i-cache-line-size = <32>;
43 d-cache-size = <32768>;
44 i-cache-size = <32768>;
[all …]
Dmpc836x_mds.dts17 /dts-v1/;
22 #address-cells = <1>;
23 #size-cells = <1>;
34 #address-cells = <1>;
35 #size-cells = <0>;
40 d-cache-line-size = <32>; // 32 bytes
41 i-cache-line-size = <32>; // 32 bytes
42 d-cache-size = <32768>; // L1, 32K
43 i-cache-size = <32768>; // L1, 32K
44 timebase-frequency = <66000000>;
[all …]
Dmpc8568mds.dts12 /include/ "fsl/mpc8568si-pre.dtsi"
38 #address-cells = <1>;
39 #size-cells = <1>;
40 compatible = "cfi-flash";
42 bank-width = <2>;
43 device-width = <2>;
47 #address-cells = <1>;
48 #size-cells = <1>;
49 compatible = "fsl,mpc8568mds-bcsr";
53 bcsr5: gpio-controller@11 {
[all …]
/linux-3.3/drivers/spi/
Dspi-pl022.c2 * A driver for the ARM PL022 PrimeCell SSP/SPI bus master.
4 * Copyright (C) 2008-2009 ST-Ericsson AB
10 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
31 #include <linux/spi/spi.h>
36 #include <linux/amba/bus.h>
41 #include <linux/dma-mapping.h>
99 * SSP Control Register 0 - SSP_CR0
117 * SSP Control Register 0 - SSP_CR1
137 * SSP Status Register - SSP_SR
146 * SSP Clock Prescale Register - SSP_CPSR
[all …]
Dspi-bfin-sport.c2 * SPI bus via the Blackfin SPORT peripheral
6 * Copyright 2009-2011 Analog Devices Inc.
8 * Licensed under the GPL-2 or later.
22 #include <linux/spi/spi.h>
31 #define DRV_NAME "bfin-sport-spi"
32 #define DRV_DESC "SPI bus via the Blackfin SPORT"
37 MODULE_ALIAS("platform:bfin-sport-spi");
58 /* SPI framework hookup */
61 /* Regs base of SPI controller */
91 void *rx; member
[all …]
Dspi-orion.c2 * Marvell Orion SPI controller driver
5 * Copyright (C) 2007-2008 Marvell Ltd.
18 #include <linux/spi/spi.h>
19 #include <linux/spi/orion_spi.h>
55 return orion_spi->base + reg; in spi_reg()
91 return -EINVAL; in orion_spi_set_transfer_size()
97 static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed) in orion_spi_baudrate_set() argument
105 orion_spi = spi_master_get_devdata(spi->master); in orion_spi_baudrate_set()
107 tclk_hz = orion_spi->spi_info->tclk; in orion_spi_baudrate_set()
118 return -EINVAL; in orion_spi_baudrate_set()
[all …]
Dspi-topcliff-pch.c2 * SPI bus driver for the Topcliff PCH used by Intel SoCs
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
23 #include <linux/spi/spi.h>
26 #include <linux/spi/spidev.h>
35 #define PCH_SPCR 0x00 /* SPI control register */
36 #define PCH_SPBRR 0x04 /* SPI baud rate register */
37 #define PCH_SPSR 0x08 /* SPI status register */
38 #define PCH_SPDWR 0x0C /* SPI write data register */
39 #define PCH_SPDRR 0x10 /* SPI read data register */
41 #define PCH_SRST 0x1C /* SPI reset register */
[all …]
Dspi-au1550.c2 * au1550 psc spi controller driver
4 * will not work on au1000, au1100 and au1500 (no full spi controller there)
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
32 #include <linux/spi/spi.h>
33 #include <linux/spi/spi_bitbang.h>
34 #include <linux/dma-mapping.h>
36 #include <asm/mach-au1x00/au1000.h>
37 #include <asm/mach-au1x00/au1xxx_psc.h>
38 #include <asm/mach-au1x00/au1xxx_dbdma.h>
40 #include <asm/mach-au1x00/au1550_spi.h>
[all …]
Dspi-s3c64xx.c25 #include <linux/dma-mapping.h>
27 #include <linux/spi/spi.h>
30 #include <plat/s3c64xx-spi.h>
32 /* Registers and bit-fields */
75 #define S3C64XX_SPI_ACT(c) writel(0, (c)->regs + S3C64XX_SPI_SLAVE_SEL)
78 (c)->regs + S3C64XX_SPI_SLAVE_SEL)
114 #define S3C64XX_SPI_ST_TRLCNTZ(v, i) ((((v) >> (i)->rx_lvl_offset) & \
115 (((i)->fifo_lvl_mask + 1))) \
118 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & (1 << (i)->tx_st_done)) ? 1 : 0)
119 #define TX_FIFO_LVL(v, i) (((v) >> 6) & (i)->fifo_lvl_mask)
[all …]
/linux-3.3/arch/arm/mach-at91/
Dboard-pcontrol-g20.c17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 * copied and adjusted from board-stamp9g20.c
21 * by Peter Gsellmann <pgsellmann@portner-elektronik.at>
27 #include <linux/w1-gpio.h>
29 #include <asm/mach-types.h>
44 /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) piggyback A2 */ in pcontrol_g20_init_early()
48 /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) isolated RS485 X5 */ in pcontrol_g20_init_early()
52 /* USART2 on ttyS3. (Rx, Tx) 9bit-Bus Multidrop-mode X4 */ in pcontrol_g20_init_early()
98 /* configure chip-select 4 (IO compatible to 8051 X4 ) */ in add_device_pcontrol()
100 /* configure chip-select 7 (FerroRAM 256KiBx16bit MR2A16A D4 ) */ in add_device_pcontrol()
[all …]
Dboard-sam9260ek.c2 * linux/arch/arm/mach-at91/board-sam9260ek.c
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 #include <linux/spi/spi.h>
29 #include <linux/spi/at73c213.h>
36 #include <asm/mach-types.h>
58 /* DBGU on ttyS0. (Rx & Tx only) */ in ek_init_early()
61 /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ in ek_init_early()
66 /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ in ek_init_early()
78 .vbus_pin = {-EINVAL, -EINVAL},
79 .overcurrent_pin= {-EINVAL, -EINVAL},
[all …]
Dboard-sam9g20ek.c17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 #include <linux/spi/spi.h>
27 #include <linux/spi/at73c213.h>
37 #include <asm/mach-types.h>
69 /* DBGU on ttyS0. (Rx & Tx only) */ in ek_init_early()
72 /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ in ek_init_early()
77 /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ in ek_init_early()
89 .vbus_pin = {-EINVAL, -EINVAL},
90 .overcurrent_pin= {-EINVAL, -EINVAL},
98 .pullup_pin = -EINVAL, /* pull-up driven by UDC */
[all …]
Dboard-sam9263ek.c2 * linux/arch/arm/mach-at91/board-sam9263ek.c
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 #include <linux/spi/spi.h>
29 #include <linux/spi/ads7846.h>
39 #include <asm/mach-types.h>
61 /* DBGU on ttyS0. (Rx & Tx only) */ in ek_init_early()
64 /* USART0 on ttyS1. (Rx, Tx, RTS, CTS) */ in ek_init_early()
77 .overcurrent_pin= {-EINVAL, -EINVAL},
85 .pullup_pin = -EINVAL, /* pull-up driven by UDC */
124 * SPI devices.
[all …]
Dboard-sam9m10g45ek.c2 * Board-specific setup code for the AT91SAM9M10G45 Evaluation Kit family
4 * Covers: * AT91SAM9G45-EKES board
5 * * AT91SAM9M10G45-EK board
22 #include <linux/spi/spi.h>
28 #include <linux/atmel-mci.h>
34 #include <asm/mach-types.h>
55 /* DGBU on ttyS0. (Rx & Tx only) */ in ek_init_early()
58 /* USART0 not connected on the -EK board */ in ek_init_early()
59 /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ in ek_init_early()
72 .overcurrent_pin= {-EINVAL, -EINVAL},
[all …]
Dboard-sam9261ek.c2 * linux/arch/arm/mach-at91/board-sam9261ek.c
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 #include <linux/spi/spi.h>
29 #include <linux/spi/ads7846.h>
30 #include <linux/spi/at73c213.h>
40 #include <asm/mach-types.h>
65 /* DBGU on ttyS0. (Rx & Tx only) */ in ek_init_early()
133 /* Configure chip-select 2 (DM9000) */ in ek_add_device_dm9000()
139 /* Configure Interrupt pin as input, no pull-up */ in ek_add_device_dm9000()
154 .vbus_pin = {-EINVAL, -EINVAL},
[all …]
/linux-3.3/drivers/net/ethernet/micrel/
Dks8851.c27 #include <linux/spi/spi.h>
32 * struct ks8851_rxctrl - KS8851 driver rx control
33 * @mchash: Multicast hash-table data.
38 * such as the multicast hash-filter and the receive register settings. This
50 * union ks8851_tx_hdr - tx header data
52 * @txw: The header as 16bit, little-endian words
64 * struct ks8851_net - KS8851 driver private data
66 * @spidev: The spi device we're bound to.
70 * @rxctrl: RX settings for @rxctrl_work.
73 * @rxctrl_work: Work queue for updating RX mode and multicast lists
[all …]
/linux-3.3/arch/blackfin/mach-bf527/include/mach/
DdefBF522.h2 * Copyright 2007-2010 Analog Devices Inc.
4 * Licensed under the ADI BSD license or the GPL-2 (or later)
11 /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF52x */
16 /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
25 /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
38 /* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
48 /* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
54 /* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
64 /* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
67 #define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
[all …]
Danomaly.h4 * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
8 * Copyright 2004-2011 Analog Devices Inc.
14 * - Revision F, 05/23/2011; ADSP-BF526 Blackfin Processor Anomaly List
15 * - Revision I, 05/23/2011; ADSP-BF527 Blackfin Processor Anomaly List
21 /* We do not support old silicon - sorry */
41 /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
45 /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
49 /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
51 /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
55 /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
[all …]
/linux-3.3/arch/blackfin/mach-bf518/include/mach/
DdefBF512.h2 * Copyright 2008-2010 Analog Devices Inc.
4 * Licensed under the ADI BSD license or the GPL-2 (or later)
11 /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF51x */
14 /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
22 /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
35 /* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */
45 /* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
51 /* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
61 /* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
64 #define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
[all …]
/linux-3.3/arch/arm/mach-u300/
Dcore.c3 * arch/arm/mach-u300/core.c
6 * Copyright (C) 2007-2010 ST-Ericsson SA
20 #include <linux/amba/bus.h>
30 #include <linux/dma-mapping.h>
43 #include <mach/gpio-u300.h>
47 #include "spi.h"
105 .end = U300_UART0_BASE + SZ_4K - 1,
129 .end = U300_UART1_BASE + SZ_4K - 1,
143 .end = U300_EMIF_CFG_BASE + SZ_4K - 1,
151 * the APP SPI bus.
[all …]
/linux-3.3/drivers/net/ethernet/sfc/
Dnic.h3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2011 Solarflare Communications Inc.
14 #include <linux/i2c-algo-bit.h>
18 #include "spi.h"
33 return efx->type->revision; in efx_nic_rev()
69 * struct falcon_board_type - board operations and type information
74 * @init_phy: Do board-specific PHY initialisation
77 * @monitor: Board-specific health check function
91 * struct falcon_board - board information
95 * @i2c_adap: I2C adapter for on-board peripherals
[all …]
/linux-3.3/drivers/net/ethernet/intel/ixgbe/
Dixgbe_common.c4 Copyright(c) 1999 - 2012 Intel Corporation.
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
67 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
70 * Starts the hardware by filling the bus info structure and media type, clears
80 hw->phy.media_type = hw->mac.ops.get_media_type(hw); in ixgbe_start_hw_generic()
83 hw->phy.ops.identify(hw); in ixgbe_start_hw_generic()
86 hw->mac.ops.clear_vfta(hw); in ixgbe_start_hw_generic()
89 hw->mac.ops.clear_hw_cntrs(hw); in ixgbe_start_hw_generic()
[all …]
/linux-3.3/arch/blackfin/mach-bf537/include/mach/
DdefBF534.h2 * Copyright 2005-2010 Analog Devices Inc.
4 * Licensed under the ADI BSD license or the GPL-2 (or later)
13 /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
21 /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
33 /* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
38 /* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
47 /* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
50 #define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
52 #define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
61 /* SPI Controller (0xFFC00500 - 0xFFC005FF) */
[all …]
/linux-3.3/arch/blackfin/mach-bf533/include/mach/
DdefBF532.h2 * System & MMR bit and Address definitions for ADSP-BF532
4 * Copyright 2005-2010 Analog Devices Inc.
6 * Licensed under the ADI BSD license or the GPL-2 (or later)
15 /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
17 #define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
18 #define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
19 #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
20 #define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
21 #define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
24 /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
[all …]

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