Lines Matching +full:spi +full:- +full:rx +full:- +full:bus +full:- +full:width
4 * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
8 * Copyright 2004-2011 Analog Devices Inc.
14 * - Revision F, 05/23/2011; ADSP-BF526 Blackfin Processor Anomaly List
15 * - Revision I, 05/23/2011; ADSP-BF527 Blackfin Processor Anomaly List
21 /* We do not support old silicon - sorry */
41 /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
45 /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
49 /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
51 /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
55 /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
83 /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
93 /* 8-Bit NAND Flash Boot Mode Not Functional */
123 /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
161 /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
193 /* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
201 /* USB Rx DMA Hang */
205 /* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */
223 /* The CODEC Zero-Cross Detect Feature is not Functional */
225 /* SPI Master Boot Can Fail Under Certain Conditions */
233 /* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */