Searched +full:spi +full:- +full:max +full:- +full:frequency (Results 1 – 10 of 10) sorted by relevance
4 * Copyright (c) 2017-2020 Subbaraya Sundeep <sundeep.lkml@gmail.com>28 #include "system/address-spaces.h"29 #include "hw/char/serial-mm.h"30 #include "hw/arm/msf2-soc.h"32 #include "hw/qdev-clock.h"48 * eSRAM max size is 80k without SECDED(Single error correction and66 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); in m2sxxx_soc_initfn()68 object_initialize_child(obj, "sysreg", &s->sysreg, TYPE_MSF2_SYSREG); in m2sxxx_soc_initfn()70 object_initialize_child(obj, "timer", &s->timer, TYPE_MSS_TIMER); in m2sxxx_soc_initfn()73 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_MSS_SPI); in m2sxxx_soc_initfn()[all …]
28 #include "hw/adc/zynq-xadc.h"31 #include "qemu/error-report.h"36 #include "hw/qdev-clock.h"41 #include "target/arm/cpu-qom.h"44 #define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9")47 /* board base frequency: 33.333333 MHz */112 rom_add_blob_fixed("board-setup", board_setup_blob, in zynq_write_board_setup()125 object_property_set_int(OBJECT(dev), "phy-addr", 7, &error_abort); in gem_init()138 SSIBus *spi; in zynq_init_spi_flashes() local144 dev = qdev_new(is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi"); in zynq_init_spi_flashes()[all …]
2 * ARM mach-virt emulation23 * + we want to present a very stripped-down minimalist platform,41 #include "hw/vfio/vfio-calxeda-xgmac.h"42 #include "hw/vfio/vfio-amd-xgbe.h"57 #include "qemu/error-report.h"59 #include "hw/pci-host/gpex.h"60 #include "hw/virtio/virtio-pci.h"61 #include "hw/core/sysbus-fdt.h"62 #include "hw/platform-bus.h"63 #include "hw/qdev-properties.h"[all …]
2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu15 * 5) OTP (One-Time Programmable) memory with stored serial number18 * 8) SPI0 connected to an SPI flash39 #include "qemu/error-report.h"65 /* CLINT timebase frequency */99 uint64_t mem_size = ms->ram_size; in create_fdt()111 "sifive,plic-1.0.0", "riscv,plic0" in create_fdt()114 fdt = ms->fdt = create_device_tree(&s->fdt_size); in create_fdt()122 "sifive,hifive-unleashed-a00"); in create_fdt()[all …]
4 * Copyright (c) 2018-2021 BALATON Zoltan17 #include "hw/or-irq.h"18 #include "hw/pci-host/mv64361.h"22 #include "hw/qdev-properties.h"28 #include "hw/fw-path-provider.h"31 #include "qemu/error-report.h"34 #include "system/address-spaces.h"35 #include "qom/qom-qobject.h"55 #define H_PRIVILEGE -3 /* Caller not privileged */56 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */[all …]
4 * Copyright (c) 2016-2024, IBM Corporation.6 * SPDX-License-Identifier: GPL-2.0-or-later45 #include "target/ppc/mmu-hash64.h"47 #include "hw/pci-host/pnv_phb.h"48 #include "hw/pci-host/pnv_phb3.h"49 #include "hw/pci-host/pnv_phb4.h"52 #include "hw/qdev-properties.h"58 #include "hw/char/serial-isa.h"69 #define PNOR_FILE_NAME "pnv-pnor.bin"79 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); in pnv_chip_core_typename()[all …]
2 * ASPEED AST2400 SMC Controller (SPI Flash Only)31 #include "qemu/error-report.h"37 #include "hw/qdev-properties.h"55 #define CONF_FLASH_TYPE_SPI 0x2 /* AST2600 is SPI only */59 #define CTRL_EXTENDED4 4 /* 32 bit addressing for SPI */60 #define CTRL_EXTENDED3 3 /* 32 bit addressing for SPI */61 #define CTRL_EXTENDED2 2 /* 32 bit addressing for SPI */62 #define CTRL_EXTENDED1 1 /* 32 bit addressing for SPI */63 #define CTRL_EXTENDED0 0 /* 32 bit addressing for SPI */80 (!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_ADDR_BYTE0_DISABLE_SHIFT + (i)))))[all …]
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5 * eMMC emulation defined in "JEDEC Standard No. 84-A43"9 * Copyright (c) 2018 Philippe Mathieu-Daudé <f4bug@amsat.org>40 #include "system/block-backend.h"45 #include "hw/qdev-properties.h"46 #include "hw/qdev-properties-system.h"47 #include "qemu/error-report.h"50 #include "qemu/guest-random.h"52 #include "sdmmc-internal.h"69 sd_r1b = -1,70 sd_illegal = -2,[all …]
4 Copyright(c) 1999 - 2006 Intel Corporation.23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497115 * RW - register is both readable and writable116 * RO - register is read only117 * WO - register is write only118 * R/clr - register is read only and is cleared when read119 * A - register array121 #define E1000_CTRL 0x00000 /* Device Control - RW */122 #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */[all …]