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/linux-6.8/drivers/pcmcia/
Dsoc_common.c4 integrated SOCs like the SA-11x0 and PXA2xx microprocessors.
71 printk(KERN_DEBUG "skt%u: %s: %pV", skt->nr, func, &vaf); in soc_pcmcia_debug()
89 if (!r->reg) in soc_pcmcia_regulator_set()
93 if (r->on == on) in soc_pcmcia_regulator_set()
97 ret = regulator_set_voltage(r->reg, v * 100000, v * 100000); in soc_pcmcia_regulator_set()
99 int vout = regulator_get_voltage(r->reg) / 100000; in soc_pcmcia_regulator_set()
101 dev_warn(&skt->socket.dev, in soc_pcmcia_regulator_set()
103 r == &skt->vcc ? "Vcc" : "Vpp", in soc_pcmcia_regulator_set()
107 ret = regulator_enable(r->reg); in soc_pcmcia_regulator_set()
109 ret = regulator_disable(r->reg); in soc_pcmcia_regulator_set()
[all …]
/linux-6.8/drivers/net/ethernet/microchip/sparx5/
Dsparx5_port.c1 // SPDX-License-Identifier: GPL-2.0+
31 status->an_complete = true; in decode_sgmii_word()
33 status->link = false; in decode_sgmii_word()
39 status->speed = SPEED_10; in decode_sgmii_word()
42 status->speed = SPEED_100; in decode_sgmii_word()
45 status->speed = SPEED_1000; in decode_sgmii_word()
48 status->link = false; in decode_sgmii_word()
52 status->duplex = DUPLEX_FULL; in decode_sgmii_word()
54 status->duplex = DUPLEX_HALF; in decode_sgmii_word()
59 status->link = !(lp_abil & ADVERTISE_RFAULT) && status->link; in decode_cl37_word()
[all …]
Dsparx5_port.h1 /* SPDX-License-Identifier: GPL-2.0+ */
69 port - 12 : port - 44; in sparx5_port_dev_index()
70 return (port - 56); in sparx5_port_dev_index()
92 int speed; member
103 int sparx5_port_fwd_urg(struct sparx5 *sparx5, u32 speed);
110 u8 map[SPARX5_PORT_QOS_PCP_DEI_COUNT]; member
114 u16 map[SPX5_PRIOS]; member
119 u16 map[SPX5_PRIOS * SPARX5_PORT_QOS_DP_NUM]; member
124 u8 map[SPARX5_PORT_QOS_DSCP_COUNT]; member
128 struct sparx5_port_qos_pcp_map map; member
[all …]
/linux-6.8/drivers/net/ethernet/microchip/lan966x/
Dlan966x_port.c1 // SPDX-License-Identifier: GPL-2.0+
17 value = (MULTIPLIER_BIT - 1); in lan966x_wm_enc()
27 struct lan966x *lan966x = port->lan966x; in lan966x_port_link_down()
35 lan966x, AFI_PORT_CFG(port->chip_port)); in lan966x_port_link_down()
39 val = lan_rd(lan966x, AFI_PORT_FRM_OUT(port->chip_port)); in lan966x_port_link_down()
46 pr_err("AFI timeout chip port %u", port->chip_port); in lan966x_port_link_down()
56 lan966x, DEV_CLOCK_CFG(port->chip_port)); in lan966x_port_link_down()
61 lan966x, DEV_MAC_ENA_CFG(port->chip_port)); in lan966x_port_link_down()
66 lan966x, QSYS_SW_PORT_MODE(port->chip_port)); in lan966x_port_link_down()
71 lan966x, QSYS_PORT_MODE(port->chip_port)); in lan966x_port_link_down()
[all …]
/linux-6.8/Documentation/devicetree/bindings/hwmon/
Dgpio-fan.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/hwmon/gpio-fan.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
14 const: gpio-fan
18 Specifies the pins that map to bits in the control value,
19 ordered MSB-->LSB.
23 alarm-gpios:
26 gpio-fan,speed-map:
[all …]
/linux-6.8/drivers/usb/dwc2/
Dhcd_queue.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * hcd_queue.c - DesignWare HS OTG Controller host queuing routines
5 * Copyright (C) 2004-2013 Synopsys, Inc.
17 #include <linux/dma-mapping.h>
35 * dwc2_periodic_channel_available() - Checks that a channel is available for a
47 * non-periodic transactions in dwc2_periodic_channel_available()
52 num_channels = hsotg->params.host_channels; in dwc2_periodic_channel_available()
53 if ((hsotg->periodic_channels + hsotg->non_periodic_channels < in dwc2_periodic_channel_available()
54 num_channels) && (hsotg->periodic_channels < num_channels - 1)) { in dwc2_periodic_channel_available()
57 dev_dbg(hsotg->dev, in dwc2_periodic_channel_available()
[all …]
/linux-6.8/drivers/hwmon/
Dgpio-fan.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * gpio-fan.c - Hwmon driver for fans connected to GPIO lines.
39 struct gpio_fan_speed *speed; member
56 sysfs_notify(&fan_data->hwmon_dev->kobj, NULL, "fan1_alarm"); in fan_alarm_notify()
57 kobject_uevent(&fan_data->hwmon_dev->kobj, KOBJ_CHANGE); in fan_alarm_notify()
64 schedule_work(&fan_data->alarm_work); in fan_alarm_irq_handler()
75 gpiod_get_value_cansleep(fan_data->alarm_gpio)); in fan1_alarm_show()
83 struct device *dev = fan_data->dev; in fan_alarm_init()
89 alarm_irq = gpiod_to_irq(fan_data->alarm_gpio); in fan_alarm_init()
93 INIT_WORK(&fan_data->alarm_work, fan_alarm_notify); in fan_alarm_init()
[all …]
/linux-6.8/Documentation/devicetree/bindings/phy/
Dnvidia,tegra194-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
Drealtek,usb2phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Stanley Chang <stanley_chang@realtek.com>
21 Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on some
23 XHCI controller#0 -- usb2phy -- phy#0
24 |- usb3phy -- phy#0
25 XHCI controller#1 -- usb2phy -- phy#0
26 XHCI controller#2 -- usb2phy -- phy#0
27 |- usb3phy -- phy#0
[all …]
/linux-6.8/sound/usb/
Dproc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
18 /* convert our full speed USB rate into sampling rate in Hz */
24 /* convert our high speed USB rate into sampling rate in Hz */
35 struct snd_usb_audio *chip = entry->private_data; in proc_audio_usbbus_read()
36 if (!atomic_read(&chip->shutdown)) in proc_audio_usbbus_read()
37 snd_iprintf(buffer, "%03d/%03d\n", chip->dev->bus->busnum, chip->dev->devnum); in proc_audio_usbbus_read()
42 struct snd_usb_audio *chip = entry->private_data; in proc_audio_usbid_read()
43 if (!atomic_read(&chip->shutdown)) in proc_audio_usbid_read()
45 USB_ID_VENDOR(chip->usb_id), in proc_audio_usbid_read()
46 USB_ID_PRODUCT(chip->usb_id)); in proc_audio_usbid_read()
[all …]
/linux-6.8/drivers/i2c/busses/
Di2c-designware-core.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
191 * struct dw_i2c_dev - private i2c-designware data
193 * @map: IO registers map
194 * @sysmap: System controller registers map
202 * @get_clk_rate_khz: callback to retrieve IP specific bus speed
223 * @rx_outstanding: current master-rx elements in tx fifo
226 * @ss_hcnt: standard speed HCNT value
227 * @ss_lcnt: standard speed LCNT value
228 * @fs_hcnt: fast speed HCNT value
229 * @fs_lcnt: fast speed LCNT value
[all …]
Di2c-designware-master.c1 // SPDX-License-Identifier: GPL-2.0-or-later
25 #include "i2c-designware-core.h"
34 regmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2); in i2c_dw_configure_fifo_master()
35 regmap_write(dev->map, DW_IC_RX_TL, 0); in i2c_dw_configure_fifo_master()
38 regmap_write(dev->map, DW_IC_CON, dev->master_cfg); in i2c_dw_configure_fifo_master()
45 struct i2c_timings *t = &dev->timings; in i2c_dw_set_timings_master()
54 ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, &comp_param1); in i2c_dw_set_timings_master()
59 /* Set standard and fast speed dividers for high/low periods */ in i2c_dw_set_timings_master()
60 sda_falling_time = t->sda_fall_ns ?: 300; /* ns */ in i2c_dw_set_timings_master()
61 scl_falling_time = t->scl_fall_ns ?: 300; /* ns */ in i2c_dw_set_timings_master()
[all …]
Di2c-designware-common.c1 // SPDX-License-Identifier: GPL-2.0-or-later
29 #include "i2c-designware-core.h"
59 "incorrect slave-transmitter mode configuration",
66 *val = readl(dev->base + reg); in dw_reg_read()
75 writel(val, dev->base + reg); in dw_reg_write()
84 *val = swab32(readl(dev->base + reg)); in dw_reg_read_swab()
93 writel(swab32(val), dev->base + reg); in dw_reg_write_swab()
102 *val = readw(dev->base + reg) | in dw_reg_read_word()
103 (readw(dev->base + reg + 2) << 16); in dw_reg_read_word()
112 writew(val, dev->base + reg); in dw_reg_write_word()
[all …]
/linux-6.8/usr/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
11 space-separated list of directories and files for building the
21 See <file:Documentation/driver-api/early-userspace/early_userspace_support.rst> for more details.
36 int "User ID to map to 0 (user root)"
41 (-1 = current user) will be owned by root in the resulting image.
46 int "Group ID to map to 0 (group root)"
51 (-1 = current group) will be owned by root in the resulting image.
112 prompt "Built-in initramfs compression mode"
118 decompression speed. Compression speed is only relevant
119 when building a kernel. Decompression speed is relevant at
[all …]
/linux-6.8/net/ethtool/
Dcommon.c1 // SPDX-License-Identifier: GPL-2.0-only
12 [NETIF_F_SG_BIT] = "tx-scatter-gather",
13 [NETIF_F_IP_CSUM_BIT] = "tx-checksum-ipv4",
14 [NETIF_F_HW_CSUM_BIT] = "tx-checksum-ip-generic",
15 [NETIF_F_IPV6_CSUM_BIT] = "tx-checksum-ipv6",
17 [NETIF_F_FRAGLIST_BIT] = "tx-scatter-gather-fraglist",
18 [NETIF_F_HW_VLAN_CTAG_TX_BIT] = "tx-vlan-hw-insert",
20 [NETIF_F_HW_VLAN_CTAG_RX_BIT] = "rx-vlan-hw-parse",
21 [NETIF_F_HW_VLAN_CTAG_FILTER_BIT] = "rx-vlan-filter",
22 [NETIF_F_HW_VLAN_STAG_TX_BIT] = "tx-vlan-stag-hw-insert",
[all …]
/linux-6.8/Documentation/devicetree/bindings/pci/
Dintel-gw-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rahul Tanwar <rtanwar@maxlinear.com>
16 const: intel,lgm-pcie
18 - compatible
21 - $ref: /schemas/pci/snps,dw-pcie.yaml#
26 - const: intel,lgm-pcie
27 - const: snps,dw-pcie
[all …]
Dtoshiba,visconti-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/toshiba,visconti-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
16 - $ref: /schemas/pci/snps,dw-pcie.yaml#
20 const: toshiba,visconti-pcie
24 - description: Data Bus Interface (DBI) registers.
25 - description: PCIe configuration space region.
26 - description: Visconti specific additional registers.
[all …]
Dti,j721e-pci-host.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - const: ti,j721e-pcie-host
17 - const: ti,j784s4-pcie-host
18 - description: PCIe controller in AM64
20 - const: ti,am64-pcie-host
[all …]
Dti,am65-pci-host.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,am65-pci-host.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: /schemas/pci/pci-bus.yaml#
19 - ti,am654-pcie-rc
20 - ti,keystone-pcie
25 reg-names:
[all …]
/linux-6.8/drivers/net/ethernet/ti/icssg/
Dicssg_config.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com
15 /* TX IPG Values to be set for 100M link speed. These values are
77 * struct map - ICSSG Queue Map
83 struct map { struct
90 /* Hardware queue map for ICSSG */ argument
91 static const struct map hwq_map[2][ICSSG_NUM_OTHER_QUEUES] = {
111 struct prueth *prueth = emac->prueth; in icssg_config_mii_init()
115 mii_rt = prueth->mii_rt; in icssg_config_mii_init()
133 if (emac->phy_if == PHY_INTERFACE_MODE_MII && slice == ICSS_MII0) in icssg_config_mii_init()
[all …]
/linux-6.8/Documentation/devicetree/bindings/regulator/
Dmaxim,max8952.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: regulator.yaml#
19 max8952,default-mode:
25 max8952,dvs-mode-microvolt:
35 max8952,en-gpio:
40 max8952,ramp-speed:
45 Voltage ramp speed, values map to:
[all …]
/linux-6.8/arch/powerpc/boot/dts/
Drainier.dts15 /dts-v1/;
18 #address-cells = <2>;
19 #size-cells = <1>;
22 dcr-parent = <&{/cpus/cpu@0}>;
34 #address-cells = <1>;
35 #size-cells = <0>;
41 clock-frequency = <0>; /* Filled in by zImage */
42 timebase-frequency = <0>; /* Filled in by zImage */
43 i-cache-line-size = <32>;
44 d-cache-line-size = <32>;
[all …]
/linux-6.8/drivers/net/dsa/mv88e6xxx/
Dport.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
24 int addr = chip->info->port_base_addr + port; in mv88e6xxx_port_read()
32 int addr = chip->info->port_base_addr + port; in mv88e6xxx_port_wait_bit()
40 int addr = chip->info->port_base_addr + port; in mv88e6xxx_port_write()
72 * For port's MAC speed, ForceSpd (or SpdValue) bits 1:0 program the value.
111 dev_dbg(chip->dev, "p%d: delay RXCLK %s, TXCLK %s\n", port, in mv88e6xxx_port_set_rgmii_delay()
122 return -EOPNOTSUPP; in mv88e6352_port_set_rgmii_delay()
131 return -EOPNOTSUPP; in mv88e6390_port_set_rgmii_delay()
140 return -EOPNOTSUPP; in mv88e6320_port_set_rgmii_delay()
[all …]
/linux-6.8/drivers/net/ethernet/hisilicon/
Dhip04_eth.c1 // SPDX-License-Identifier: GPL-2.0-or-later
155 #define TX_NEXT(N) (((N) + 1) & (TX_DESC_NUM-1))
156 #define RX_NEXT(N) (((N) + 1) & (RX_DESC_NUM-1))
165 #define DRV_NAME "hip04-ether"
218 unsigned int speed; member
244 struct regmap *map; member
253 return (head - tail) % TX_DESC_NUM; in tx_count()
256 static void hip04_config_port(struct net_device *ndev, u32 speed, u32 duplex) in hip04_config_port() argument
261 priv->speed = speed; in hip04_config_port()
262 priv->duplex = duplex; in hip04_config_port()
[all …]
/linux-6.8/drivers/net/ethernet/cavium/thunder/
Dthunder_xcv.c1 // SPDX-License-Identifier: GPL-2.0-only
70 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
72 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
75 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
77 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
81 /* Configure DLL - enable or bypass in xcv_init_hw()
84 cfg = readq_relaxed(xcv->reg_base + XCV_DLL_CTL); in xcv_init_hw()
87 writeq_relaxed(cfg, xcv->reg_base + XCV_DLL_CTL); in xcv_init_hw()
92 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
94 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
[all …]

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