1 // SPDX-License-Identifier: GPL-2.0
4  * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com
15 /* TX IPG Values to be set for 100M link speed. These values are
77  * struct map - ICSSG Queue Map
83 struct map {  struct
90 /* Hardware queue map for ICSSG */  argument
91 static const struct map hwq_map[2][ICSSG_NUM_OTHER_QUEUES] = {
111 	struct prueth *prueth = emac->prueth;  in icssg_config_mii_init()
115 	mii_rt = prueth->mii_rt;  in icssg_config_mii_init()
133 	if (emac->phy_if == PHY_INTERFACE_MODE_MII && slice == ICSS_MII0)  in icssg_config_mii_init()
135 	else if (emac->phy_if != PHY_INTERFACE_MODE_MII && slice == ICSS_MII1)  in icssg_config_mii_init()
145 	struct regmap *miig_rt = prueth->miig_rt;  in icssg_miig_queues_init()
146 	void __iomem *smem = prueth->shram.va;  in icssg_miig_queues_init()
173 		const struct map *mp;  in icssg_miig_queues_init()
178 		if (mp->special) {  in icssg_miig_queues_init()
190 			pdword[0] |= mp->flags;  in icssg_miig_queues_init()
191 			pdaddr = mp->pd_addr_start + i * pd_size;  in icssg_miig_queues_init()
194 			queue = mp->queue;  in icssg_miig_queues_init()
203 	struct prueth *prueth = emac->prueth;  in icssg_config_ipg()
206 	switch (emac->speed) {  in icssg_config_ipg()
208 		icssg_mii_update_ipg(prueth->mii_rt, slice, MII_RT_TX_IPG_1G);  in icssg_config_ipg()
211 		icssg_mii_update_ipg(prueth->mii_rt, slice, MII_RT_TX_IPG_100M);  in icssg_config_ipg()
215 		icssg_mii_update_ipg(prueth->mii_rt, slice, MII_RT_TX_IPG_100M);  in icssg_config_ipg()
219 		netdev_err(emac->ndev, "Unsupported link speed\n");  in icssg_config_ipg()
229 	p = emac->dram.va + MGR_R30_CMD_OFFSET;  in emac_r30_cmd_init()
232 		writel(EMAC_NONE, &p->cmd[i]);  in emac_r30_cmd_init()
241 	p = emac->dram.va + MGR_R30_CMD_OFFSET;  in emac_r30_is_done()
244 		cmd = readl(&p->cmd[i]);  in emac_r30_is_done()
256 	struct prueth *prueth = emac->prueth;  in prueth_emac_buffer_setup()
265 	addr = lower_32_bits(prueth->msmcram.pa);  in prueth_emac_buffer_setup()
270 		dev_warn(prueth->dev, "buffer pool needs to be 64KB aligned\n");  in prueth_emac_buffer_setup()
271 		return -EINVAL;  in prueth_emac_buffer_setup()
274 	bpool_cfg = emac->dram.va + BUFFER_POOL_0_ADDR_OFFSET;  in prueth_emac_buffer_setup()
292 	/* Pre-emptible RX buffer queue */  in prueth_emac_buffer_setup()
293 	rxq_ctx = emac->dram.va + HOST_RX_Q_PRE_CONTEXT_OFFSET;  in prueth_emac_buffer_setup()
295 		writel(addr, &rxq_ctx->start[i]);  in prueth_emac_buffer_setup()
298 	writel(addr, &rxq_ctx->end);  in prueth_emac_buffer_setup()
301 	rxq_ctx = emac->dram.va + HOST_RX_Q_EXP_CONTEXT_OFFSET;  in prueth_emac_buffer_setup()
303 		writel(addr, &rxq_ctx->start[i]);  in prueth_emac_buffer_setup()
306 	writel(addr, &rxq_ctx->end);  in prueth_emac_buffer_setup()
318 	if (prueth->emacs_initialized)  in icssg_init_emac_mode()
321 	regmap_update_bits(prueth->miig_rt, FDB_GEN_CFG1,  in icssg_init_emac_mode()
323 	regmap_write(prueth->miig_rt, FDB_GEN_CFG2, 0);  in icssg_init_emac_mode()
325 	icssg_class_set_host_mac_addr(prueth->miig_rt, mac);  in icssg_init_emac_mode()
330 	void __iomem *config = emac->dram.va + ICSSG_CONFIG_OFFSET;  in icssg_config()
339 	emac->speed = SPEED_1000;  in icssg_config()
340 	emac->duplex = DUPLEX_FULL;  in icssg_config()
341 	if (!phy_interface_mode_is_rgmii(emac->phy_if)) {  in icssg_config()
342 		emac->speed = SPEED_100;  in icssg_config()
343 		emac->duplex = DUPLEX_FULL;  in icssg_config()
345 	regmap_update_bits(prueth->miig_rt, ICSSG_CFG_OFFSET,  in icssg_config()
347 	icssg_miig_set_interface_mode(prueth->miig_rt, slice, emac->phy_if);  in icssg_config()
350 	icssg_update_rgmii_cfg(prueth->miig_rt, emac);  in icssg_config()
353 	pruss_cfg_gpimode(prueth->pruss, prueth->pru_id[slice],  in icssg_config()
357 	pruss_cfg_xfr_enable(prueth->pruss, PRU_TYPE_PRU, true);  in icssg_config()
358 	pruss_cfg_xfr_enable(prueth->pruss, PRU_TYPE_RTU, true);  in icssg_config()
361 	pru_rproc_set_ctable(prueth->pru[slice], PRU_C28, 0x100 << 8);  in icssg_config()
362 	pru_rproc_set_ctable(prueth->rtu[slice], PRU_C28, 0x100 << 8);  in icssg_config()
363 	pru_rproc_set_ctable(prueth->txpru[slice], PRU_C28, 0x100 << 8);  in icssg_config()
366 	writew(emac->rx_flow_id_base, &flow_cfg->rx_base_flow);  in icssg_config()
367 	writew(0, &flow_cfg->mgm_base_flow);  in icssg_config()
407 	int ret = -ETIMEDOUT;  in emac_set_port_state()
411 	p = emac->dram.va + MGR_R30_CMD_OFFSET;  in emac_set_port_state()
414 		netdev_err(emac->ndev, "invalid port command\n");  in emac_set_port_state()
415 		return -EINVAL;  in emac_set_port_state()
419 	mutex_lock(&emac->cmd_lock);  in emac_set_port_state()
422 		writel(emac_r32_bitmask[cmd].cmd[i], &p->cmd[i]);  in emac_set_port_state()
428 	if (ret == -ETIMEDOUT)  in emac_set_port_state()
429 		netdev_err(emac->ndev, "timeout waiting for command done\n");  in emac_set_port_state()
431 	mutex_unlock(&emac->cmd_lock);  in emac_set_port_state()
440 	if (!emac->half_duplex)  in icssg_config_half_duplex()
444 	writel(val, emac->dram.va + HD_RAND_SEED_OFFSET);  in icssg_config_half_duplex()
451 	switch (emac->speed) {  in icssg_config_set_speed()
463 		netdev_err(emac->ndev, "Unsupported link speed\n");  in icssg_config_set_speed()
467 	if (emac->duplex == DUPLEX_HALF)  in icssg_config_set_speed()
470 	writeb(fw_speed, emac->dram.va + PORT_LINK_SPEED_OFFSET);  in icssg_config_set_speed()