| /linux-5.10/Documentation/devicetree/bindings/ata/ |
| D | sata-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/sata-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common Properties for Serial AT attachment (SATA) controllers
10 - Linus Walleij <linus.walleij@linaro.org>
14 AT attachment (SATA) storage devices. It doesn't constitute a device tree
18 The SATA controller-specific device tree bindings are responsible for
23 pattern: "^sata(@.*)?$"
25 Specifies the host controller node. SATA host controller nodes are named
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| D | ahci-platform.txt | 1 * AHCI SATA Controller
3 SATA nodes are defined to describe on-chip Serial ATA controllers.
4 Each SATA controller should have its own node.
6 It is possible, but not required, to represent each port as a sub-node.
7 It allows to enable each port independently when dealing with multiple
11 - compatible : compatible string, one of:
12 - "brcm,iproc-ahci"
13 - "hisilicon,hisi-ahci"
14 - "cavium,octeon-7130-ahci"
15 - "ibm,476gtr-ahci"
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| D | brcm,sata-brcm.txt | 3 SATA nodes are defined to describe on-chip Serial ATA controllers.
4 Each SATA controller should have its own node.
7 - compatible : should be one or more of
8 "brcm,bcm7216-ahci"
9 "brcm,bcm7425-ahci"
10 "brcm,bcm7445-ahci"
11 "brcm,bcm-nsp-ahci"
12 "brcm,sata3-ahci"
13 "brcm,bcm63138-ahci"
14 - reg : register mappings for AHCI and SATA_TOP_CTRL
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| D | faraday,ftide010.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
15 platform. The controller can do PIO modes 0 through 4, Multi-word DMA
19 SATA bridge in order to support SATA. This is why a phandle to that
22 The timing properties are unique per-SoC, not per-board.
27 - const: faraday,ftide010
28 - items:
29 - const: cortina,gemini-pata
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| D | sata_highbank.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Calxeda AHCI SATA Controller
10 The Calxeda SATA controller mostly conforms to the AHCI interface
15 - Andre Przywara <andre.przywara@arm.com>
19 const: calxeda,hb-ahci
27 dma-coherent: true
29 calxeda,pre-clocks:
35 calxeda,post-clocks:
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| D | fsl-sata.txt | 1 * Freescale 8xxx/3.0 Gb/s SATA nodes
3 SATA nodes are defined to describe on-chip Serial ATA controllers.
4 Each SATA port should have its own node.
7 - compatible : compatible list, contains 2 entries, first is
8 "fsl,CHIP-sata", where CHIP is the processor
10 "fsl,pq-sata"
11 - interrupts : <interrupt mapping for SATA IRQ>
12 - cell-index : controller index.
19 - reg : <registers mapping>
22 sata@18000 {
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| /linux-5.10/arch/arm64/boot/dts/broadcom/stingray/ |
| D | stingray-sata.dtsi | 4 * Copyright(c) 2016-2017 Broadcom. All rights reserved.
33 sata {
34 compatible = "simple-bus";
35 #address-cells = <1>;
36 #size-cells = <1>;
40 compatible = "brcm,iproc-ahci", "generic-ahci";
42 reg-names = "ahci";
44 #address-cells = <1>;
45 #size-cells = <0>;
48 sata0_port0: sata-port@0 {
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| /linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | phy-miphy365x.txt | 5 for SATA and PCIe.
8 - compatible : Should be "st,miphy365x-phy"
9 - st,syscfg : Phandle / integer array property. Phandle of sysconfig group
11 an entry for each port sub-node, specifying the control
14 Required nodes : A sub-node is required for each channel the controller
16 'reg' and 'reg-names' properties are used inside these
20 Required properties (port (child) node):
21 - #phy-cells : Should be 1 (See second example)
22 Cell after port phandle is device type from:
23 - PHY_TYPE_SATA
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| D | nvidia,tegra124-xusb-padctl.txt | 11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
27 "port" is typically used to denote the physical USB receptacle. The device
28 tree binding in this document uses the term "port" to refer to the logical
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| D | phy-miphy28lp.txt | 5 for SATA, PCIe or USB3.
8 - compatible : Should be "st,miphy28lp-phy".
9 - st,syscfg : Should be a phandle of the system configuration register group
10 which contain the SATA, PCIe or USB3 mode setting bits.
12 Required nodes : A sub-node is required for each channel the controller
14 'reg' and 'reg-names' properties are used inside these
18 Required properties (port (child) node):
19 - #phy-cells : Should be 1 (See second example)
20 Cell after port phandle is device type from:
21 - PHY_TYPE_SATA
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| D | brcm-sata-phy.txt | 4 - compatible: should be one or more of
5 "brcm,bcm7216-sata-phy"
6 "brcm,bcm7425-sata-phy"
7 "brcm,bcm7445-sata-phy"
8 "brcm,iproc-ns2-sata-phy"
9 "brcm,iproc-nsp-sata-phy"
10 "brcm,phy-sata3"
11 "brcm,iproc-sr-sata-phy"
12 "brcm,bcm63138-sata-phy"
13 - address-cells: should be 1
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| /linux-5.10/drivers/scsi/mvsas/ |
| D | mv_defs.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
28 /* driver compile-time configuration */
30 MVS_TX_RING_SZ = 1024, /* TX ring size (12-bit) */
31 MVS_RX_RING_SZ = 1024, /* RX ring size (12-bit) */
32 /* software requires power-of-2
40 MVS_ATA_CMD_SZ = 96, /* SATA command table buffer size */
43 MVS_SOC_CAN_QUEUE = MVS_SOC_SLOTS - 2,
76 INT_SAS_SATA = (1U << 0), /* SAS/SATA event */
78 /* MVS_GBL_PORT_TYPE */ /* shl for ports 1-3 */
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| /linux-5.10/drivers/phy/tegra/ |
| D | xusb-tegra210.c | 1 // SPDX-License-Identifier: GPL-2.0-only
25 ((x) ? (11 + ((x) - 1) * 6) : 0)
259 /* must be called under padctl->lock */
262 struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie); in tegra210_pex_uphy_enable()
267 if (pcie->enable > 0) { in tegra210_pex_uphy_enable()
268 pcie->enable++; in tegra210_pex_uphy_enable()
272 err = clk_prepare_enable(pcie->pll); in tegra210_pex_uphy_enable()
276 err = reset_control_deassert(pcie->rst); in tegra210_pex_uphy_enable()
355 err = -ETIMEDOUT; in tegra210_pex_uphy_enable()
374 err = -ETIMEDOUT; in tegra210_pex_uphy_enable()
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| D | xusb-tegra124.c | 1 // SPDX-License-Identifier: GPL-2.0-only
229 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_enable()
231 if (padctl->enable++ > 0) in tegra124_xusb_padctl_enable()
251 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_enable()
259 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_disable()
261 if (WARN_ON(padctl->enable == 0)) in tegra124_xusb_padctl_disable()
264 if (--padctl->enable > 0) in tegra124_xusb_padctl_disable()
284 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_disable()
291 struct tegra_xusb_usb3_port *port; in tegra124_usb3_save_context() local
295 port = tegra_xusb_find_usb3_port(padctl, index); in tegra124_usb3_save_context()
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| /linux-5.10/drivers/scsi/aic94xx/ |
| D | aic94xx_dev.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Aic94xx SAS/SATA DDB management
16 #define FIND_FREE_DDB(_ha) find_first_zero_bit((_ha)->hw_prof.ddb_bitmap, \
17 (_ha)->hw_prof.max_ddbs)
18 #define SET_DDB(_ddb, _ha) set_bit(_ddb, (_ha)->hw_prof.ddb_bitmap)
19 #define CLEAR_DDB(_ddb, _ha) clear_bit(_ddb, (_ha)->hw_prof.ddb_bitmap)
26 if (ddb >= asd_ha->hw_prof.max_ddbs) { in asd_get_ddb()
27 ddb = -ENOMEM; in asd_get_ddb()
67 struct asd_ha_struct *asd_ha = dev->port->ha->lldd_ha; in asd_set_ddb_type()
68 int ddb = (int) (unsigned long) dev->lldd_dev; in asd_set_ddb_type()
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| /linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | mvebu-gated-clock.txt | 12 -----------------------------------
20 15 sata0 SATA Host 0
25 30 sata1 SATA Host 0
29 -----------------------------------
37 14 sata0_link SATA 0 Link
38 15 sata0_core SATA 0 Core
43 20 sata1_link SATA 1 Link
44 21 sata1_core SATA 1 Core
49 28 crypto0_enc Cryptographic Unit Port 0 Encryption
50 29 crypto0_core Cryptographic Unit Port 0 Core
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| /linux-5.10/drivers/phy/samsung/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
6 tristate "Exynos SoC series Display Port PHY driver"
12 Support for Display Port PHY found on Samsung Exynos SoCs.
15 tristate "S5P/Exynos SoC series MIPI CSI-2/DSI PHY driver"
21 Support for MIPI CSI-2 and MIPI DSI DPHY found on Samsung S5P
77 are available - device and host.
93 tristate "Exynos5250 Sata SerDes/PHY driver"
102 Enable this to support SATA SerDes/Phy found on Samsung's
103 Exynos5250 based SoCs.This SerDes/Phy supports SATA 1.5 Gb/s,
104 SATA 3.0 Gb/s, SATA 6.0 Gb/s speeds. It supports one SATA host
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| /linux-5.10/drivers/phy/broadcom/ |
| D | phy-brcm-sata.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
27 /* The older SATA PHY registers duplicated per port registers within the map,
28 * rather than having a separate map per port.
189 static inline void __iomem *brcm_sata_ctrl_base(struct brcm_sata_port *port) in brcm_sata_ctrl_base() argument
191 struct brcm_sata_phy *priv = port->phy_priv; in brcm_sata_ctrl_base()
194 switch (priv->version) { in brcm_sata_ctrl_base()
199 dev_err(priv->dev, "invalid phy version\n"); in brcm_sata_ctrl_base()
203 return priv->ctrl_base + (port->portnum * size); in brcm_sata_ctrl_base()
206 static void brcm_sata_phy_wr(struct brcm_sata_port *port, u32 bank, in brcm_sata_phy_wr() argument
209 struct brcm_sata_phy *priv = port->phy_priv; in brcm_sata_phy_wr()
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| /linux-5.10/drivers/ata/ |
| D | libata-sata.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * SATA specific part of ATA helper library
5 * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
6 * Copyright 2003-2004 Jeff Garzik
17 #include "libata-transport.h"
28 * sata_scr_valid - test whether SCRs are accessible
41 struct ata_port *ap = link->ap; in sata_scr_valid()
43 return (ap->flags & ATA_FLAG_SATA) && ap->ops->scr_read; in sata_scr_valid()
48 * sata_scr_read - read SCR register of the specified port
54 * guaranteed to succeed if @link is ap->link, the cable type of
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| D | ata_piix.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ata_piix.c - Intel PATA/SATA controllers
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
14 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
15 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
19 * as Documentation/driver-api/libata.rst
32 * change little except in gaining more modes until SATA arrives. This
40 * PIIX4 errata #9 - Only on ultra obscure hw
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| /linux-5.10/drivers/scsi/isci/ |
| D | probe_roms.h | 7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
102 * by phys in the supplied port.
103 * - A value of 1 indicates generation 1 (i.e. 1.5 Gb/s).
104 * - A value of 2 indicates generation 2 (i.e. 3.0 Gb/s).
105 * - A value of 3 indicates generation 3 (i.e. 6.0 Gb/s).
197 /* Allowed PORT configuration modes APC Automatic PORT configuration mode is
199 * for any PORT. i.e. There are no phys assigned to any of the ports at start.
200 * MPC Manual PORT configuration mode is defined by the OEM configuration
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| /linux-5.10/arch/arm/boot/dts/ |
| D | gemini.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/clock/cortina,gemini-clock.h>
8 #include <dt-bindings/reset/cortina,gemini-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
16 compatible = "simple-bus";
17 interrupt-parent = <&intcon>;
20 compatible = "cortina,gemini-flash", "cfi-flash";
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| D | armada-370-dlink-dns327l.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for D-Link DNS-327L
12 /dts-v1/;
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include "armada-370.dtsi"
19 model = "D-Link DNS-327L";
22 "marvell,armada-370-xp";
25 stdout-path = &uart0;
38 internal-regs {
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| /linux-5.10/Documentation/ABI/testing/ |
| D | sysfs-ata | 8 -------------------------------
10 For each port, a directory ataX is created where X is the ata_port_id of the
11 port. The device parent is the ata host device.
20 nr_pmp_links: (RO) If a SATA Port Multiplier (PM) is
23 idle_irq: (RO) Number of IRQ received by the port while
32 (RO) Host local port number. While registering host controller,
33 port numbers are tracked based upon number of ports available on
35 persistent links in /dev/disk/by-path.
38 -------------------------------
40 Behind each port, there is a ata_link. If there is a SATA PM in the topology, 15
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| /linux-5.10/drivers/scsi/libsas/ |
| D | sas_ata.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Support for SATA devices on Serial Attached SCSI (SAS) controllers
32 if (ts->resp == SAS_TASK_UNDELIVERED) in sas_to_ata_err()
35 /* ts->resp == SAS_TASK_COMPLETE */ in sas_to_ata_err()
37 switch (ts->stat) { in sas_to_ata_err()
65 __func__, ts->stat); in sas_to_ata_err()
83 struct ata_queued_cmd *qc = task->uldd_task; in sas_ata_task_done()
84 struct domain_device *dev = task->dev; in sas_ata_task_done()
85 struct task_status_struct *stat = &task->task_status; in sas_ata_task_done()
86 struct ata_task_resp *resp = (struct ata_task_resp *)stat->buf; in sas_ata_task_done()
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