scsi/mvsas/mv_defs.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
7  * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
28 /* driver compile-time configuration */
30 	MVS_TX_RING_SZ		= 1024,	/* TX ring size (12-bit) */
31 	MVS_RX_RING_SZ		= 1024, /* RX ring size (12-bit) */
32 					/* software requires power-of-2
40 	MVS_ATA_CMD_SZ		= 96,	/* SATA command table buffer size */
43 	MVS_SOC_CAN_QUEUE	= MVS_SOC_SLOTS - 2,
76 	INT_SAS_SATA		= (1U << 0),	/* SAS/SATA event */
78 	/* MVS_GBL_PORT_TYPE */			/* shl for ports 1-3 */
79 	SATA_TARGET		= (1U << 16),	/* port0 SATA target enable */
80 	MODE_AUTO_DET_PORT7 = (1U << 15),	/* port0 SAS/SATA autodetect */
92 	MODE_SAS_PORT7_MASK = (1U << 7),  /* port0 SAS(1), SATA(0) mode */
134 						/* shl for ports 1-3 */
146 	TXQ_CMD_STP		= 3,		/* STP/SATA protocol */
155 	TXQ_SRS_SHIFT		= 20,		/* SATA register set */
172 	MCH_PRD_LEN_SHIFT	= 16,		/* 16-bit PRD table len */
189 	MCH_PASSTHRU		= (1U << 12),	/* pass-through (SSP) */
194 	MCH_RESET		= (1U << 7),	/* Reset (STP/SATA) */
195 	MCH_FPDMA		= (1U << 6),	/* First party DMA (STP/SATA) */
196 	MCH_ATAPI		= (1U << 5),	/* ATAPI (STP/SATA) */
197 	MCH_BIST		= (1U << 4),	/* BIST activate (STP/SATA) */
198 	MCH_PMP_MASK		= 0xf,		/* PMP from cmd FIS (STP/SATA)*/
200 	CCTL_RST		= (1U << 5),	/* port logic reset */
208 	/* MVS_Px_SER_CTLSTAT (per-phy control) */
215 	/* MVS_Px_INT_STAT, MVS_Px_INT_MASK (per-phy events) */
220 	PHYEV_AN		= (1U << 18),	/* SATA async notification */
223 	PHYEV_POOF		= (1U << 12),	/* phy ready from 1 -> 0 */
229 	PHYEV_PORT_SEL		= (1U << 6),	/* port selector present */
238 	PCS_EN_SATA_REG_SHIFT	= (16),		/* Enable SATA Register Set */
239 	PCS_EN_PORT_XMT_SHIFT	= (12),		/* Enable Port Transmit */
244 	PCS_SELF_CLEAR		= (1U << 5),	/* self-clearing int mode */
246 	PCS_CMD_STOP_ERR	= (1U << 3),	/* cmd stop-on-err enable */
250 	/* Port n Attached Device Info */
264 	/* Port n PHY Status */
287 /* SAS/SATA configuration port registers, aka phy registers */
295 	PHYR_SATA_CTL		= 0x18,	/* SATA control */
297 	PHYR_SATA_SIG0	= 0x20,	/*port SATA signature FIS(Byte 0-3) */
298 	PHYR_SATA_SIG1	= 0x24,	/*port SATA signature FIS(Byte 4-7) */
299 	PHYR_SATA_SIG2	= 0x28,	/*port SATA signature FIS(Byte 8-11) */
300 	PHYR_SATA_SIG3	= 0x2c,	/*port SATA signature FIS(Byte 12-15) */
301 	PHYR_R_ERR_COUNT	= 0x30, /* port R_ERR count register */
302 	PHYR_CRC_ERR_COUNT	= 0x34, /* port CRC error count register */
303 	PHYR_WIDE_PORT	= 0x38,	/* wide port participating */
307 	CONFIG_ID_FRAME0       = 0x100, /* Port device ID frame register 0 */
308 	CONFIG_ID_FRAME1       = 0x104, /* Port device ID frame register 1 */
309 	CONFIG_ID_FRAME2       = 0x108, /* Port device ID frame register 2 */
310 	CONFIG_ID_FRAME3       = 0x10c, /* Port device ID frame register 3 */
311 	CONFIG_ID_FRAME4       = 0x110, /* Port device ID frame register 4 */
312 	CONFIG_ID_FRAME5       = 0x114, /* Port device ID frame register 5 */
313 	CONFIG_ID_FRAME6       = 0x118, /* Port device ID frame register 6 */
340 	CMD_PORT_SEL_COUNT	= 0x140, /* port selector count register */
344 	CMD_PORT_MEM_CTL0	= 0x150, /* Port Memory Control 0 */
345 	CMD_PORT_MEM_CTL1	= 0x154, /* Port Memory Control 1 */
346 	CMD_SATA_PORT_MEM_CTL0	= 0x158, /* SATA Port Memory Control 0 */
347 	CMD_SATA_PORT_MEM_CTL1	= 0x15c, /* SATA Port Memory Control 1 */
352 	CMD_PORT_MEM_BIST_CTL	= 0x170, /* Port Memory BIST Control */
353 	CMD_PORT_MEM_BIST_STAT0 = 0x174, /* Port Memory BIST Status 0 */
354 	CMD_PORT_MEM_BIST_STAT1 = 0x178, /* Port Memory BIST Status 1 */
374 	CMD_PORT_LAYER_TIMER1	= 0x1E0, /* Port Layer Timer 1 */
429 	TFILE_ERR	= (1U << 24),	/* SATA taskfile Error bit set */
430 	R_ERR		= (1U << 23),	/* SATA returned R_ERR prim */