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/linux-6.15/Documentation/networking/device_drivers/ethernet/intel/
Didpf.rst1 .. SPDX-License-Identifier: GPL-2.0+
17 For questions related to hardware requirements, refer to the documentation
18 supplied with your Intel adapter. All hardware requirements listed apply to use
24 For information on how to identify your adapter, and for the latest Intel
25 network drivers, refer to the Intel Support website:
33 -------
42 ---------------------
43 Link messages will not be displayed to the console if the distribution is
44 restricting system messages. In order to see network driver link messages on
45 your console, set dmesg to eight by entering the following::
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Di40e.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 1999-2018 Intel Corporation.
13 - Overview
14 - Identifying Your Adapter
15 - Intel(R) Ethernet Flow Director
16 - Additional Configurations
17 - Known Issues
18 - Support
25 For questions related to hardware requirements, refer to the documentation
26 supplied with your Intel adapter. All hardware requirements listed apply to use
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/linux-6.15/Documentation/devicetree/bindings/net/
Dsnps,dwmac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
15 # will be able to report a warning when we have that compatible, since
16 # we will validate the node thanks to the select, but won't report it
23 - snps,dwmac
24 - snps,dwmac-3.40a
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Dnxp,s32-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright 2021-2024 NXP
4 ---
5 $id: http://devicetree.org/schemas/net/nxp,s32-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Jan Petrous (OSS) <jan.petrous@oss.nxp.com>
16 the SoC S32R45 has two instances. The devices can use RGMII/RMII/MII
18 to the embedded SerDes for SGMII connectivity.
23 - const: nxp,s32g2-dwmac
24 - items:
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Dintel,dwmac-plat.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/intel,dwmac-plat.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
17 - intel,keembay-dwmac
19 - compatible
22 - $ref: snps,dwmac.yaml#
27 - items:
28 - enum:
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Dsophgo,sg2044-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/sophgo,sg2044-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inochi Amaoto <inochiama@gmail.com>
17 - sophgo,sg2044-dwmac
19 - compatible
24 - const: sophgo,sg2044-dwmac
25 - const: snps,dwmac-5.30a
32 - description: GMAC main clock
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Dintel,ixp4xx-hss.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/intel,ixp4xx-hss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Linus Walleij <linus.walleij@linaro.org>
14 The Intel IXP4xx HSS makes use of the IXP4xx NPE (Network
15 Processing Engine) and the IXP4xx Queue Manager to process
20 const: intel,ixp4xx-hss
26 intel,npe-handle:
27 $ref: /schemas/types.yaml#/definitions/phandle-array
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/linux-6.15/Documentation/networking/devlink/
Dmlx5.rst1 .. SPDX-License-Identifier: GPL-2.0
13 .. list-table:: Generic parameters implemented
15 * - Name
16 - Mode
17 - Validation
18 * - ``enable_roce``
19 - driverinit
20 - Type: Boolean
26 * - ``io_eq_size``
27 - driverinit
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/linux-6.15/Documentation/networking/device_drivers/ethernet/huawei/
Dhinic.rst1 .. SPDX-License-Identifier: GPL-2.0
11 The driver supports a range of link-speed devices (10GbE, 25GbE, 40GbE, etc.).
14 Some HiNIC devices support SR-IOV. This driver is used for Physical Function
17 HiNIC devices support MSI-X interrupt vector for each Tx/Rx queue and
21 TCP Transmit Segmentation Offload(TSO), Receive-Side Scaling(RSS) and
28 19e5:1822 - HiNIC PF
34 hinic_dev - Implement a Logical Network device that is independent from
37 hinic_hwdev - Implement the HW details of the device and include the components
55 Asynchronous Event Queues(AEQs) - The event queues for receiving messages from
58 Application Programmable Interface commands(API CMD) - Interface for sending
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/linux-6.15/Documentation/networking/device_drivers/ethernet/freescale/
Ddpaa.rst1 .. SPDX-License-Identifier: GPL-2.0
8 - Madalin Bucur <madalin.bucur@nxp.com>
9 - Camelia Groza <camelia.groza@nxp.com>
13 - DPAA Ethernet Overview
14 - DPAA Ethernet Supported SoCs
15 - Configuring DPAA Ethernet in your kernel
16 - DPAA Ethernet Frame Processing
17 - DPAA Ethernet Features
18 - DPAA IRQ Affinity and Receive Side Scaling
19 - Debugging
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/linux-6.15/drivers/net/wireless/ralink/rt2x00/
Drt2x00queue.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
21 * Ralink PCI devices demand the Frame size to be a multiple of 128 bytes,
23 * 2432 makes sense since it is big enough to contain the maximum fragment
24 * size according to the ieee802.11 specs.
41 * @QID_RX: RX queue
42 * @QID_OTHER: None of the above (don't use, only present for completeness)
43 * @QID_BEACON: Beacon queue (value unspecified, don't send it to device)
44 * @QID_ATIM: Atim queue (value unspecified, don't send it to device)
62 * @SKBDESC_DMA_MAPPED_RX: &skb_dma field has been mapped for RX
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/linux-6.15/Documentation/networking/device_drivers/ethernet/google/
Dgve.rst1 .. SPDX-License-Identifier: GPL-2.0+
9 The GVE driver binds to a single PCI device id used by the virtual
12 +--------------+----------+---------+
16 +--------------+----------+---------+
18 +--------------+----------+---------+
19 |Sub-vendor ID | `0x1AE0` | Google |
20 +--------------+----------+---------+
21 |Sub-device ID | `0x0058` | |
22 +--------------+----------+---------+
24 +--------------+----------+---------+
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/linux-6.15/drivers/net/ethernet/intel/ixgbe/
Dixgbe_lib.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2024 Intel Corporation. */
9 * ixgbe_cache_ring_dcb_sriov - Descriptor ring to register mapping for SR-IOV
10 * @adapter: board private structure to initialize
12 * Cache the descriptor ring offsets for SR-IOV to the assigned rings. It
13 * will also try to cache the proper offsets if RSS/FCoE are enabled along
20 struct ixgbe_ring_feature *fcoe = &adapter->ring_feature[RING_F_FCOE]; in ixgbe_cache_ring_dcb_sriov()
22 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; in ixgbe_cache_ring_dcb_sriov()
25 u8 tcs = adapter->hw_tcs; in ixgbe_cache_ring_dcb_sriov()
32 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) in ixgbe_cache_ring_dcb_sriov()
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/linux-6.15/drivers/net/ethernet/intel/idpf/
Didpf_txrx.h1 /* SPDX-License-Identifier: GPL-2.0-only */
27 /* Number of descriptors in a queue should be a multiple of 32. RX queue
29 * to achieve BufQ descriptors aligned to 32
66 * given RX completion queue has descriptors. This includes _ALL_ buffer
67 * queues. E.g.: If you have two buffer queues of 512 descriptors and buffers,
68 * you have a total of 1024 buffers so your RX queue _must_ have at least that
69 * many descriptors. This macro divides a given number of RX descriptors by
70 * number of buffer queues to calculate how many descriptors each buffer queue
71 * can have without overrunning the RX queue.
74 * happen is that if hardware gets a chance to post more than ring wrap of
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Didpf.h1 /* SPDX-License-Identifier: GPL-2.0-only */
25 #define GETMAXVAL(num_bits) GENMASK((num_bits) - 1, 0)
31 #define IDPF_NUM_DFLT_MBX_Q 2 /* includes both TX and RX */
33 #define IDPF_DFLT_MBX_ID -1
34 /* maximum number of times to try before resetting mailbox */
37 ((IDPF_CTLQ_MAX_BUF_LEN - (struct_sz)) / (chunk_sz))
64 * enum idpf_state - State machine to handle bring up
68 * @__IDPF_STATE_LAST: Must be last, used to determine size
78 * enum idpf_flags - Hard reset causes.
98 * enum idpf_cap_field - Offsets into capabilities struct for specific caps
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/linux-6.15/Documentation/networking/
Ddevmem.rst1 .. SPDX-License-Identifier: GPL-2.0
16 -----------
22 - Distributed training, where ML accelerators, such as GPUs on different hosts,
25 - Distributed raw block storage applications transfer large amounts of data with
28 Typically the Device-to-Device data transfers in the network are implemented as
29 the following low-level operations: Device-to-Host copy, Host-to-Host network
30 transfer, and Host-to-Device copy.
36 Devmem TCP optimizes this use case by implementing socket APIs that enable
37 the user to receive incoming network packets directly into device memory.
39 Packet payloads go directly from the NIC to device memory.
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Diou-zcrx.rst1 .. SPDX-License-Identifier: GPL-2.0
4 io_uring zero copy Rx
10 io_uring zero copy Rx (ZC Rx) is a feature that removes kernel-to-user copy on
11 the network receive path, allowing packet data to be received directly into
12 userspace memory. This feature is different to TCP_ZEROCOPY_RECEIVE in that
13 there are no strict alignment requirements and no need to mmap()/munmap().
14 Compared to kernel bypass solutions such as e.g. DPDK, the packet headers are
20 Several NIC HW features are required for io_uring ZC Rx to work. For now the
24 -----------------
26 Required to split packets at the L4 boundary into a header and a payload.
[all …]
Dscaling.rst1 .. SPDX-License-Identifier: GPL-2.0
12 networking stack to increase parallelism and improve performance for
13 multi-processor systems.
17 - RSS: Receive Side Scaling
18 - RPS: Receive Packet Steering
19 - RFS: Receive Flow Steering
20 - Accelerated Receive Flow Steering
21 - XPS: Transmit Packet Steering
27 Contemporary NICs support multiple receive and transmit descriptor queues
28 (multi-queue). On reception, a NIC can send different packets to different
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/linux-6.15/arch/arm64/boot/dts/st/
Dstm32mp253.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
11 compatible = "arm,cortex-a35";
14 enable-method = "psci";
15 power-domains = <&CPU_PD1>;
16 power-domain-names = "psci";
20 arm-pmu {
23 interrupt-affinity = <&cpu0>, <&cpu1>;
27 CPU_PD1: power-domain-cpu1 {
28 #power-domain-cells = <0>;
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Dstm32mp233.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2025 - All Rights Reserved
11 compatible = "arm,cortex-a35";
14 enable-method = "psci";
15 power-domains = <&cpu1_pd>;
16 power-domain-names = "psci";
20 arm-pmu {
23 interrupt-affinity = <&cpu0>, <&cpu1>;
27 cpu1_pd: power-domain-cpu1 {
28 #power-domain-cells = <0>;
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/linux-6.15/drivers/net/ethernet/sfc/siena/
Dnet_driver.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2005-2013 Solarflare Communications Inc.
61 /* Checksum generation is a per-queue option in hardware, so each
62 * queue visible to the networking core is backed by two hardware TX
63 * queues. */
68 #define EFX_TXQ_TYPE_HIGHPRI 4 /* High-priority (for TC) */
70 /* HIGHPRI is Siena-only, and INNER_CSUM is EF10, so no need for both */
83 /* Size of an RX scatter buffer. Small enough to pack 2 into a 4K page,
86 #define EFX_RX_USR_BUF_SIZE (2048 - 256)
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/linux-6.15/drivers/net/
Dxen-netfront.c4 * Copyright (c) 2002-2005, K A Fraser
11 * software packages, subject to the following license:
13 * Permission is hereby granted, free of charge, to any person obtaining a copy
14 * of this source file (the "Software"), to deal in the Software without
15 * restriction, including without limitation the rights to use, copy, modify,
17 * and to permit persons to whom the Software is furnished to do so, subject to
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
28 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
67 "Maximum number of queues per virtual interface");
81 #define NETFRONT_SKB_CB(skb) ((struct netfront_cb *)((skb)->cb))
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/linux-6.15/arch/arm64/boot/dts/qcom/
Dsa8540p-ride.dts1 // SPDX-License-Identifier: BSD-3-Clause
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
13 #include "sa8540p-pmics.dtsi"
17 compatible = "qcom,sa8540p-ride", "qcom,sa8540p";
29 stdout-path = "serial0:115200n8";
34 regulators-0 {
35 compatible = "qcom,pm8150-rpmh-regulators";
36 qcom,pmic-id = "a";
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/linux-6.15/include/xen/interface/io/
Dnetif.h1 /* SPDX-License-Identifier: MIT */
5 * Unified network-device I/O interface for Xen guest OSes.
7 * Copyright (c) 2003-2004, Keir Fraser
19 * ring slots a skb can use. Netfront / netback may not work as
22 * A better approach is to add mechanism for netfront / netback to
24 * frontends, so we need to define a value which states the minimum
28 * (18), which is proved to work with most frontends. Any new backend
29 * which doesn't negotiate with frontend should expect frontend to
30 * send a valid packet using slots up to this value.
37 * If the client sends notification for rx requests then it should specify
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/linux-6.15/drivers/net/ethernet/sfc/
Dnet_driver.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2005-2013 Solarflare Communications Inc.
63 /* Checksum generation is a per-queue option in hardware, so each
64 * queue visible to the networking core is backed by two hardware TX
65 * queues. */
83 /* Size of an RX scatter buffer. Small enough to pack 2 into a 4K page,
86 #define EFX_RX_USR_BUF_SIZE (2048 - 256)
89 * of every buffer. Otherwise, we just need to ensure 4-byte
98 /* Non-standard XDP_PACKET_HEADROOM and tailroom to satisfy XDP_REDIRECT and
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