1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/intel,dwmac-plat.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Intel DWMAC glue layer
8
9maintainers:
10  - Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
11
12select:
13  properties:
14    compatible:
15      contains:
16        enum:
17          - intel,keembay-dwmac
18  required:
19    - compatible
20
21allOf:
22  - $ref: snps,dwmac.yaml#
23
24properties:
25  compatible:
26    oneOf:
27      - items:
28          - enum:
29              - intel,keembay-dwmac
30          - const: snps,dwmac-4.10a
31
32  clocks:
33    items:
34      - description: GMAC main clock
35      - description: PTP reference clock
36      - description: Tx clock
37
38  clock-names:
39    items:
40      - const: stmmaceth
41      - const: ptp_ref
42      - const: tx_clk
43
44  interrupts:
45    maxItems: 1
46
47  interrupt-names:
48    const: macirq
49
50required:
51  - compatible
52  - clocks
53  - clock-names
54
55unevaluatedProperties: false
56
57examples:
58# FIXME: Remove defines and include the correct header file
59# once it is available in mainline.
60  - |
61    #include <dt-bindings/interrupt-controller/arm-gic.h>
62    #include <dt-bindings/interrupt-controller/irq.h>
63    #define MOVISOC_KMB_PSS_GBE
64    #define MOVISOC_KMB_PSS_AUX_GBE_PTP
65    #define MOVISOC_KMB_PSS_AUX_GBE_TX
66
67    stmmac_axi_setup: stmmac-axi-config {
68        snps,lpi_en;
69        snps,wr_osr_lmt = <0x0>;
70        snps,rd_osr_lmt = <0x2>;
71        snps,blen = <0 0 0 0 16 8 4>;
72    };
73
74    mtl_rx_setup: rx-queues-config {
75        snps,rx-queues-to-use = <2>;
76        snps,rx-sched-sp;
77        queue0 {
78            snps,dcb-algorithm;
79            snps,map-to-dma-channel = <0x0>;
80            snps,priority = <0x0>;
81        };
82
83        queue1 {
84            snps,dcb-algorithm;
85            snps,map-to-dma-channel = <0x1>;
86            snps,priority = <0x1>;
87        };
88    };
89
90    mtl_tx_setup: tx-queues-config {
91        snps,tx-queues-to-use = <2>;
92        snps,tx-sched-wrr;
93        queue0 {
94           snps,weight = <0x10>;
95           snps,dcb-algorithm;
96           snps,priority = <0x0>;
97        };
98
99        queue1 {
100            snps,weight = <0x10>;
101            snps,dcb-algorithm;
102            snps,priority = <0x1>;
103        };
104    };
105
106    gmac0: ethernet@3a000000 {
107        compatible = "intel,keembay-dwmac", "snps,dwmac-4.10a";
108        interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
109        interrupt-names = "macirq";
110        reg = <0x3a000000 0x8000>;
111        snps,perfect-filter-entries = <128>;
112        phy-handle = <&eth_phy0>;
113        phy-mode = "rgmii";
114        rx-fifo-depth = <4096>;
115        tx-fifo-depth = <4096>;
116        clock-names = "stmmaceth", "ptp_ref", "tx_clk";
117        clocks = <&scmi_clk MOVISOC_KMB_PSS_GBE>,
118                 <&scmi_clk MOVISOC_KMB_PSS_AUX_GBE_PTP>,
119                 <&scmi_clk MOVISOC_KMB_PSS_AUX_GBE_TX>;
120        snps,pbl = <0x4>;
121        snps,axi-config = <&stmmac_axi_setup>;
122        snps,mtl-rx-config = <&mtl_rx_setup>;
123        snps,mtl-tx-config = <&mtl_tx_setup>;
124        snps,tso;
125
126        mdio {
127            #address-cells = <1>;
128            #size-cells = <0>;
129            compatible = "snps,dwmac-mdio";
130
131            ethernet-phy@0 {
132                reg = <0>;
133            };
134        };
135    };
136
137...
138