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/linux-6.15/arch/arm/boot/dts/st/
Dstm32f429.dtsi50 #include <dt-bindings/mfd/stm32f4-rcc.h>
101 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
123 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
145 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
167 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
189 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
205 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
221 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
241 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
255 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
[all …]
Dstm32f746.dtsi45 #include <dt-bindings/mfd/stm32f7-rcc.h>
83 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
105 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
127 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
149 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
171 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
187 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
203 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
223 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
237 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
[all …]
Dstm32h743.dtsi45 #include <dt-bindings/mfd/stm32h7-rcc.h>
77 clocks = <&rcc TIM5_CK>;
85 clocks = <&rcc LPTIM1_CK>;
113 resets = <&rcc STM32H7_APB1L_RESET(SPI2)>;
114 clocks = <&rcc SPI2_CK>;
125 resets = <&rcc STM32H7_APB1L_RESET(SPI3)>;
126 clocks = <&rcc SPI3_CK>;
135 clocks = <&rcc USART2_CK>;
143 clocks = <&rcc USART3_CK>;
151 clocks = <&rcc UART4_CK>;
[all …]
Dstm32mp151.dtsi135 clocks = <&rcc IPCC>;
140 rcc: rcc@50000000 { label
141 compatible = "st,stm32mp1-rcc", "syscon";
260 clocks = <&rcc SYSCFG>;
267 clocks = <&rcc TMPSENS>;
277 clocks = <&rcc MDMA>;
278 resets = <&rcc MDMA_R>;
289 clocks = <&rcc SDMMC1_K>;
291 resets = <&rcc SDMMC1_R>;
303 clocks = <&rcc SDMMC2_K>;
[all …]
Dstm32mp131.dtsi142 clocks = <&rcc TIM2_K>;
177 clocks = <&rcc TIM3_K>;
213 clocks = <&rcc TIM4_K>;
247 clocks = <&rcc TIM5_K>;
283 clocks = <&rcc TIM6_K>;
308 clocks = <&rcc TIM7_K>;
332 clocks = <&rcc LPTIM1_K>;
375 clocks = <&rcc SPI2_K>;
376 resets = <&rcc SPI2_R>;
400 clocks = <&rcc SPI3_K>;
[all …]
Dstm32mp133.dtsi18 clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
31 clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
44 clocks = <&rcc ADC1>, <&rcc ADC1_K>;
83 clocks = <&rcc ETH2MAC>,
84 <&rcc ETH2TX>,
85 <&rcc ETH2RX>,
86 <&rcc ETH2STP>,
87 <&rcc ETH2CK_K>;
Dstm32mp157.dtsi15 clocks = <&rcc GPU>, <&rcc GPU_K>;
17 resets = <&rcc GPU_R>;
23 clocks = <&rcc DSI>, <&clk_hse>, <&rcc DSI_PX>;
26 resets = <&rcc DSI_R>;
Dstm32f769.dtsi15 resets = <&rcc STM32F7_APB1_RESET(CAN3)>;
16 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
24 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
30 clocks = <&rcc 1 CLK_F769_DSI>, <&clk_hse>;
32 resets = <&rcc STM32F7_APB2_RESET(DSI)>;
Dstm32mp157c-ev1-scmi.dts39 clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
57 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
61 clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
80 &rcc {
81 compatible = "st,stm32mp1-rcc-secure", "syscon";
Dstm32mp157a-dk1-scmi.dts33 clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
51 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
70 &rcc {
71 compatible = "st,stm32mp1-rcc-secure", "syscon";
Dstm32mp157c-dk2-scmi.dts39 clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
57 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
76 &rcc {
77 compatible = "st,stm32mp1-rcc-secure", "syscon";
Dstm32mp157c-ed1-scmi.dts38 clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
56 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
75 &rcc {
76 compatible = "st,stm32mp1-rcc-secure", "syscon";
/linux-6.15/Documentation/devicetree/bindings/clock/
Dst,stm32-rcc.yaml4 $id: http://devicetree.org/schemas/clock/st,stm32-rcc.yaml#
13 The RCC IP is both a reset and a clock controller.
14 The reset phandle argument is the bit number within the RCC registers bank,
15 starting from RCC base address.
22 - st,stm32f42xx-rcc
23 - st,stm32f746-rcc
24 - st,stm32h743-rcc
25 - const: st,stm32-rcc
28 - st,stm32f469-rcc
29 - const: st,stm32f42xx-rcc
[all …]
Dst,stm32mp1-rcc.yaml4 $id: http://devicetree.org/schemas/clock/st,stm32mp1-rcc.yaml#
13 The RCC IP is both a reset and a clock controller.
14 RCC makes also power management (resume/supend and wakeup interrupt).
33 The index is the bit number within the RCC registers bank, starting from RCC
59 - st,stm32mp1-rcc-secure
60 - st,stm32mp1-rcc
61 - st,stm32mp13-rcc
86 - st,stm32mp1-rcc-secure
87 - st,stm32mp13-rcc
119 rcc: rcc@50000000 {
[all …]
Dst,stm32h7-rcc.txt4 The RCC IP is both a reset and a clock controller.
11 "st,stm32h743-rcc"
31 rcc: reset-clock-controller@58024400 {
32 compatible = "st,stm32h743-rcc", "st,stm32-rcc";
50 clocks = <&rcc TIM5_CK>;
59 The index is the bit number within the RCC registers bank, starting from RCC
70 resets = <&rcc STM32H7_APB1L_RESET(TIM2)>;
Dst,stm32mp25-rcc.yaml4 $id: http://devicetree.org/schemas/clock/st,stm32mp25-rcc.yaml#
13 The RCC hardware block is both a reset and a clock controller.
14 RCC makes also power management (resume/supend).
17 include/dt-bindings/clock/st,stm32mp25-rcc.h
18 include/dt-bindings/reset/st,stm32mp25-rcc.h
23 - st,stm32mp25-rcc
132 #include <dt-bindings/clock/st,stm32mp25-rcc.h>
134 rcc: clock-controller@44200000 {
135 compatible = "st,stm32mp25-rcc";
/linux-6.15/arch/arm64/boot/dts/st/
Dstm32mp251.dtsi6 #include <dt-bindings/clock/st,stm32mp25-rcc.h>
8 #include <dt-bindings/reset/st,stm32mp25-rcc.h>
245 clocks = <&rcc CK_BUS_SPI2>, <&rcc CK_KER_SPI2>;
247 resets = <&rcc SPI2_R>;
261 clocks = <&rcc CK_KER_SPI2>;
262 resets = <&rcc SPI2_R>;
275 clocks = <&rcc CK_BUS_SPI3>, <&rcc CK_KER_SPI3>;
277 resets = <&rcc SPI3_R>;
291 clocks = <&rcc CK_KER_SPI3>;
292 resets = <&rcc SPI3_R>;
[all …]
Dstm32mp231.dtsi6 #include <dt-bindings/clock/st,stm32mp25-rcc.h>
9 #include <dt-bindings/reset/st,stm32mp25-rcc.h>
232 clocks = <&rcc CK_BUS_SPI2>, <&rcc CK_KER_SPI2>;
234 resets = <&rcc SPI2_R>;
248 clocks = <&rcc CK_KER_SPI2>;
249 resets = <&rcc SPI2_R>;
262 clocks = <&rcc CK_BUS_SPI3>, <&rcc CK_KER_SPI3>;
264 resets = <&rcc SPI3_R>;
278 clocks = <&rcc CK_KER_SPI3>;
279 resets = <&rcc SPI3_R>;
[all …]
Dstm32mp233.dtsi58 clocks = <&rcc CK_ETH2_MAC>,
59 <&rcc CK_ETH2_TX>,
60 <&rcc CK_ETH2_RX>,
61 <&rcc CK_KER_ETH2PTP>,
62 <&rcc CK_ETH2_STP>,
63 <&rcc CK_KER_ETH2>;
Dstm32mp253.dtsi58 clocks = <&rcc CK_ETH2_MAC>,
59 <&rcc CK_ETH2_TX>,
60 <&rcc CK_ETH2_RX>,
61 <&rcc CK_KER_ETH2PTP>,
62 <&rcc CK_ETH2_STP>,
63 <&rcc CK_KER_ETH2>;
/linux-6.15/Documentation/devicetree/bindings/net/
Dstm32-dwmac.yaml105 select RCC clock instead of ETH_REF_CLK. OR in RGMII mode when you want to select
106 RCC clock instead of ETH_CLK125.
111 set this property in RGMII PHY when you want to select RCC clock instead of ETH_CLK125.
117 select RCC clock instead of ETH_REF_CLK.
178 clocks = <&rcc ETHMAC>,
179 <&rcc ETHTX>,
180 <&rcc ETHRX>,
181 <&rcc ETHSTP>,
182 <&rcc ETHCK_K>;
199 clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
[all …]
/linux-6.15/drivers/clk/qcom/
Dclk-rpm.c254 struct rpm_cc *rcc = r->rpm_cc; in clk_rpm_xo_prepare() local
258 mutex_lock(&rcc->xo_lock); in clk_rpm_xo_prepare()
260 value = rcc->xo_buffer_value | (QCOM_RPM_XO_MODE_ON << r->xo_offset); in clk_rpm_xo_prepare()
264 rcc->xo_buffer_value = value; in clk_rpm_xo_prepare()
267 mutex_unlock(&rcc->xo_lock); in clk_rpm_xo_prepare()
275 struct rpm_cc *rcc = r->rpm_cc; in clk_rpm_xo_unprepare() local
279 mutex_lock(&rcc->xo_lock); in clk_rpm_xo_unprepare()
281 value = rcc->xo_buffer_value & ~(QCOM_RPM_XO_MODE_ON << r->xo_offset); in clk_rpm_xo_unprepare()
285 rcc->xo_buffer_value = value; in clk_rpm_xo_unprepare()
288 mutex_unlock(&rcc->xo_lock); in clk_rpm_xo_unprepare()
[all …]
/linux-6.15/Documentation/devicetree/bindings/i2c/
Dst,stm32-i2c.yaml145 #include <dt-bindings/mfd/stm32f7-rcc.h>
153 resets = <&rcc 277>;
154 clocks = <&rcc 0 149>;
160 #include <dt-bindings/mfd/stm32f7-rcc.h>
168 resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
169 clocks = <&rcc 1 CLK_I2C1>;
175 #include <dt-bindings/mfd/stm32f7-rcc.h>
186 clocks = <&rcc I2C2_K>;
187 resets = <&rcc I2C2_R>;
/linux-6.15/Documentation/devicetree/bindings/media/
Dst,stm32mp25-csi.yaml92 #include <dt-bindings/clock/st,stm32mp25-rcc.h>
95 #include <dt-bindings/reset/st,stm32mp25-rcc.h>
100 resets = <&rcc CSI_R>;
101 clocks = <&rcc CK_KER_CSI>, <&rcc CK_KER_CSITXESC>, <&rcc CK_KER_CSIPHY>;
/linux-6.15/Documentation/devicetree/bindings/phy/
Dst,stm32mp25-combophy.yaml30 - description: ker Internal RCC reference clock for USB3 or PCIe
103 #include <dt-bindings/clock/st,stm32mp25-rcc.h>
105 #include <dt-bindings/reset/st,stm32mp25-rcc.h>
111 clocks = <&rcc CK_BUS_USB3PCIEPHY>, <&rcc CK_KER_USB3PCIEPHY>;
113 resets = <&rcc USB3PCIEPHY_R>;

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