dts/st/stm32mp231.dtsi

6 #include <dt-bindings/clock/st,stm32mp25-rcc.h>
9 #include <dt-bindings/reset/st,stm32mp25-rcc.h>
232 				clocks = <&rcc CK_BUS_SPI2>, <&rcc CK_KER_SPI2>;
234 				resets = <&rcc SPI2_R>;
248 				clocks = <&rcc CK_KER_SPI2>;
249 				resets = <&rcc SPI2_R>;
262 				clocks = <&rcc CK_BUS_SPI3>, <&rcc CK_KER_SPI3>;
264 				resets = <&rcc SPI3_R>;
278 				clocks = <&rcc CK_KER_SPI3>;
279 				resets = <&rcc SPI3_R>;
291 				clocks = <&rcc CK_KER_SPDIFRX>;
305 				clocks = <&rcc CK_KER_USART2>;
317 				clocks = <&rcc CK_KER_USART3>;
329 				clocks = <&rcc CK_KER_UART4>;
341 				clocks = <&rcc CK_KER_UART5>;
356 				clocks = <&rcc CK_KER_I2C1>;
357 				resets = <&rcc I2C1_R>;
372 				clocks = <&rcc CK_KER_I2C2>;
373 				resets = <&rcc I2C2_R>;
388 				clocks = <&rcc CK_KER_I2C7>;
389 				resets = <&rcc I2C7_R>;
401 				clocks = <&rcc CK_KER_USART6>;
414 				clocks = <&rcc CK_BUS_SPI1>, <&rcc CK_KER_SPI1>;
416 				resets = <&rcc SPI1_R>;
430 				clocks = <&rcc CK_KER_SPI1>;
431 				resets = <&rcc SPI1_R>;
445 				clocks = <&rcc CK_KER_SPI4>;
446 				resets = <&rcc SPI4_R>;
460 				clocks = <&rcc CK_KER_SPI5>;
461 				resets = <&rcc SPI5_R>;
475 				clocks = <&rcc CK_BUS_SAI1>;
478 				resets = <&rcc SAI1_R>;
486 					clocks = <&rcc CK_KER_SAI1>;
496 					clocks = <&rcc CK_KER_SAI1>;
509 				clocks = <&rcc CK_BUS_SAI2>;
512 				resets = <&rcc SAI2_R>;
520 					clocks = <&rcc CK_KER_SAI2>;
530 					clocks = <&rcc CK_KER_SAI2>;
543 				clocks = <&rcc CK_BUS_SAI3>;
546 				resets = <&rcc SAI3_R>;
554 					clocks = <&rcc CK_KER_SAI3>;
564 					clocks = <&rcc CK_KER_SAI3>;
575 				clocks = <&rcc CK_KER_USART1>;
589 				clocks = <&rcc CK_BUS_SAI4>;
592 				resets = <&rcc SAI4_R>;
600 					clocks = <&rcc CK_KER_SAI4>;
610 					clocks = <&rcc CK_KER_SAI4>;
621 				clocks = <&rcc CK_KER_UART7>;
632 				clocks = <&clk_rcbsec>, <&rcc CK_BUS_RNG>;
634 				resets = <&rcc RNG_R>;
645 				clocks = <&rcc CK_KER_SPI8>;
646 				resets = <&rcc SPI8_R>;
661 				clocks = <&rcc CK_KER_I2C8>;
662 				resets = <&rcc I2C8_R>;
674 				resets = <&rcc CSI_R>;
675 				clocks = <&rcc CK_KER_CSI>, <&rcc CK_KER_CSITXESC>,
676 					 <&rcc CK_KER_CSIPHY>;
686 				resets = <&rcc DCMIPP_R>;
687 				clocks = <&rcc CK_BUS_DCMIPP>, <&rcc CK_KER_CSI>;
698 				clocks = <&rcc CK_KER_SDMMC1 >;
700 				resets = <&rcc SDMMC1_R>;
720 				clocks = <&rcc CK_ETH1_MAC>,
721 					 <&rcc CK_ETH1_TX>,
722 					 <&rcc CK_ETH1_RX>,
723 					 <&rcc CK_KER_ETH1PTP>,
724 					 <&rcc CK_ETH1_STP>,
725 					 <&rcc CK_KER_ETH1>;
774 		rcc: clock-controller@44200000 {  label
775 			compatible = "st,stm32mp25-rcc";