Lines Matching full:rcc
142 clocks = <&rcc TIM2_K>;
177 clocks = <&rcc TIM3_K>;
213 clocks = <&rcc TIM4_K>;
247 clocks = <&rcc TIM5_K>;
283 clocks = <&rcc TIM6_K>;
308 clocks = <&rcc TIM7_K>;
332 clocks = <&rcc LPTIM1_K>;
375 clocks = <&rcc SPI2_K>;
376 resets = <&rcc SPI2_R>;
400 clocks = <&rcc SPI3_K>;
401 resets = <&rcc SPI3_R>;
414 clocks = <&rcc SPDIF_K>;
427 clocks = <&rcc USART3_K>;
428 resets = <&rcc USART3_R>;
440 clocks = <&rcc UART4_K>;
441 resets = <&rcc UART4_R>;
453 clocks = <&rcc UART5_K>;
454 resets = <&rcc UART5_R>;
468 clocks = <&rcc I2C1_K>;
469 resets = <&rcc I2C1_R>;
486 clocks = <&rcc I2C2_K>;
487 resets = <&rcc I2C2_R>;
502 clocks = <&rcc UART7_K>;
503 resets = <&rcc UART7_R>;
515 clocks = <&rcc UART8_K>;
516 resets = <&rcc UART8_R>;
534 clocks = <&rcc TIM1_K>;
575 clocks = <&rcc TIM8_K>;
610 clocks = <&rcc USART6_K>;
611 resets = <&rcc USART6_R>;
634 clocks = <&rcc SPI1_K>;
635 resets = <&rcc SPI1_R>;
651 resets = <&rcc SAI1_R>;
658 clocks = <&rcc SAI1_K>;
668 clocks = <&rcc SAI1_K>;
682 resets = <&rcc SAI2_R>;
689 clocks = <&rcc SAI2_K>;
699 clocks = <&rcc SAI2_K>;
709 clocks = <&rcc DFSDM_K>;
747 clocks = <&rcc DMA1>;
748 resets = <&rcc DMA1_R>;
765 clocks = <&rcc DMA2>;
766 resets = <&rcc DMA2_R>;
775 clocks = <&rcc DMAMUX1>;
776 resets = <&rcc DMAMUX1_R>;
783 rcc: rcc@50000000 { label
784 compatible = "st,stm32mp13-rcc", "syscon";
902 clocks = <&rcc SYSCFG>;
909 clocks = <&rcc LPTIM4_K>;
930 clocks = <&rcc LPTIM5_K>;
951 clocks = <&rcc DTS>;
961 clocks = <&rcc MDMA>;
970 clocks = <&rcc CRC1>;
977 clocks = <&usbphyc>, <&rcc USBH>;
978 resets = <&rcc USBH_R>;
986 clocks = <&usbphyc>, <&rcc USBH>;
987 resets = <&rcc USBH_R>;
996 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
1047 clocks = <&rcc ADC2>, <&rcc ADC2_K>;
1090 clocks = <&rcc USBO_K>;
1092 resets = <&rcc USBO_R>;
1109 clocks = <&rcc USART1_K>;
1110 resets = <&rcc USART1_R>;
1123 clocks = <&rcc USART2_K>;
1124 resets = <&rcc USART2_R>;
1149 clocks = <&rcc SPI4_K>;
1150 resets = <&rcc SPI4_R>;
1164 clocks = <&rcc SPI5_K>;
1165 resets = <&rcc SPI5_R>;
1181 clocks = <&rcc I2C3_K>;
1182 resets = <&rcc I2C3_R>;
1200 clocks = <&rcc I2C4_K>;
1201 resets = <&rcc I2C4_R>;
1219 clocks = <&rcc I2C5_K>;
1220 resets = <&rcc I2C5_R>;
1239 clocks = <&rcc TIM12_K>;
1269 clocks = <&rcc TIM13_K>;
1299 clocks = <&rcc TIM14_K>;
1329 clocks = <&rcc TIM15_K>;
1364 clocks = <&rcc TIM16_K>;
1397 clocks = <&rcc TIM17_K>;
1429 clocks = <&rcc LPTIM2_K>;
1464 clocks = <&rcc LPTIM3_K>;
1492 clocks = <&rcc HASH1>;
1493 resets = <&rcc HASH1_R>;
1503 clocks = <&rcc RNG1_K>;
1504 resets = <&rcc RNG1_R>;
1519 clocks = <&rcc FMC_K>;
1520 resets = <&rcc FMC_R>;
1553 clocks = <&rcc QSPI_K>;
1554 resets = <&rcc QSPI_R>;
1564 clocks = <&rcc SDMMC1_K>;
1566 resets = <&rcc SDMMC1_R>;
1579 clocks = <&rcc SDMMC2_K>;
1581 resets = <&rcc SDMMC2_R>;
1601 clocks = <&rcc ETH1MAC>,
1602 <&rcc ETH1TX>,
1603 <&rcc ETH1RX>,
1604 <&rcc ETH1STP>,
1605 <&rcc ETH1CK_K>;
1627 clocks = <&rcc USBPHY_K>;
1628 resets = <&rcc USBPHY_R>;
1664 clocks = <&rcc GPIOA>;
1676 clocks = <&rcc GPIOB>;
1688 clocks = <&rcc GPIOC>;
1700 clocks = <&rcc GPIOD>;
1712 clocks = <&rcc GPIOE>;
1724 clocks = <&rcc GPIOF>;
1736 clocks = <&rcc GPIOG>;
1748 clocks = <&rcc GPIOH>;
1760 clocks = <&rcc GPIOI>;