| /linux-6.15/drivers/spi/ |
| D | spi-bcm-qspi.c | 25 #include "spi-bcm-qspi.h"
255 static inline bool has_bspi(struct bcm_qspi *qspi) in has_bspi() argument
257 return qspi->bspi_mode; in has_bspi()
261 static inline bool bcm_qspi_has_fastbr(struct bcm_qspi *qspi) in bcm_qspi_has_fastbr() argument
263 if (!has_bspi(qspi) && in bcm_qspi_has_fastbr()
264 ((qspi->mspi_maj_rev >= 1) && in bcm_qspi_has_fastbr()
265 (qspi->mspi_min_rev >= 5))) in bcm_qspi_has_fastbr()
272 static inline bool bcm_qspi_has_sysclk_108(struct bcm_qspi *qspi) in bcm_qspi_has_sysclk_108() argument
274 if (!has_bspi(qspi) && (qspi->mspi_spcr3_sysclk || in bcm_qspi_has_sysclk_108()
275 ((qspi->mspi_maj_rev >= 1) && in bcm_qspi_has_sysclk_108()
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| D | spi-ti-qspi.c | 3 * TI QSPI driver
126 static inline unsigned long ti_qspi_read(struct ti_qspi *qspi, in ti_qspi_read() argument
129 return readl(qspi->base + reg); in ti_qspi_read()
132 static inline void ti_qspi_write(struct ti_qspi *qspi, in ti_qspi_write() argument
135 writel(val, qspi->base + reg); in ti_qspi_write()
140 struct ti_qspi *qspi = spi_controller_get_devdata(spi->controller); in ti_qspi_setup() local
144 dev_dbg(qspi->dev, "host busy doing other transfers\n"); in ti_qspi_setup()
148 if (!qspi->host->max_speed_hz) { in ti_qspi_setup()
149 dev_err(qspi->dev, "spi max frequency not defined\n"); in ti_qspi_setup()
153 spi->max_speed_hz = min(spi->max_speed_hz, qspi->host->max_speed_hz); in ti_qspi_setup()
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| D | spi-stm32-qspi.c | 131 struct stm32_qspi *qspi = (struct stm32_qspi *)dev_id; in stm32_qspi_irq() local
134 cr = readl_relaxed(qspi->io_base + QSPI_CR); in stm32_qspi_irq()
135 sr = readl_relaxed(qspi->io_base + QSPI_SR); in stm32_qspi_irq()
140 writel_relaxed(cr, qspi->io_base + QSPI_CR); in stm32_qspi_irq()
141 complete(&qspi->match_completion); in stm32_qspi_irq()
149 writel_relaxed(cr, qspi->io_base + QSPI_CR); in stm32_qspi_irq()
150 complete(&qspi->data_completion); in stm32_qspi_irq()
166 static int stm32_qspi_tx_poll(struct stm32_qspi *qspi, in stm32_qspi_tx_poll() argument
184 ret = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, in stm32_qspi_tx_poll()
188 dev_err(qspi->dev, "fifo timeout (len:%d stat:%#x)\n", in stm32_qspi_tx_poll()
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| D | spi-microchip-core-qspi.c | 3 * Microchip coreQSPI QSPI controller driver
25 * QSPI Control register mask defines
43 * QSPI Frames register mask defines
55 * QSPI Interrupt Enable register mask defines
65 * QSPI Status register mask defines
84 /* QSPI ready time out value */
88 * QSPI Register offsets.
103 * struct mchp_coreqspi - Defines qspi driver instance
104 * @regs: Virtual address of the QSPI controller registers
105 * @clk: QSPI Operating clock
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| D | spi-qpic-snand.c | 31 /* QSPI NAND config reg bits */
174 struct qpic_spi_nand *qspi = ecceng_to_qspi(eng); in nand_to_qcom_snand() local
176 return qspi->snandc; in nand_to_qcom_snand()
218 struct qpic_ecc *qecc = snandc->qspi->ecc; in qcom_spi_ooblayout_ecc()
234 struct qpic_ecc *qecc = snandc->qspi->ecc; in qcom_spi_ooblayout_free()
259 snandc->qspi->num_cw = cwperpage; in qcom_spi_ecc_init_ctx_pipelined()
264 snandc->qspi->oob_buf = kzalloc(mtd->writesize + mtd->oobsize, in qcom_spi_ecc_init_ctx_pipelined()
266 if (!snandc->qspi->oob_buf) { in qcom_spi_ecc_init_ctx_pipelined()
271 memset(snandc->qspi->oob_buf, 0xff, mtd->writesize + mtd->oobsize); in qcom_spi_ecc_init_ctx_pipelined()
274 snandc->qspi->mtd = mtd; in qcom_spi_ecc_init_ctx_pipelined()
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| D | spi-zynq-qspi.c | 41 * QSPI Configuration Register bit Masks
44 * of the QSPI controller
57 * QSPI Configuration Register - Baud rate and target select
67 * QSPI Interrupt Registers bit Masks
72 #define ZYNQ_QSPI_IXR_RX_OVERFLOW_MASK BIT(0) /* QSPI RX FIFO Overflow */
73 #define ZYNQ_QSPI_IXR_TXNFULL_MASK BIT(2) /* QSPI TX FIFO Overflow */
74 #define ZYNQ_QSPI_IXR_TXFULL_MASK BIT(3) /* QSPI TX FIFO is full */
75 #define ZYNQ_QSPI_IXR_RXNEMTY_MASK BIT(4) /* QSPI RX FIFO Not Empty */
76 #define ZYNQ_QSPI_IXR_RXF_FULL_MASK BIT(5) /* QSPI RX FIFO is full */
77 #define ZYNQ_QSPI_IXR_TXF_UNDRFLOW_MASK BIT(6) /* QSPI TX FIFO Underflow */
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| D | spi-zynqmp-gqspi.c | 3 * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
25 /* Generic QSPI register offsets */
160 * struct qspi_platform_data - zynqmp qspi platform data structure
168 * struct zynqmp_qspi - Defines qspi driver instance
170 * @regs: Virtual address of the QSPI controller registers
184 * @mode: Defines the mode in which QSPI is operating
188 * @has_tapdelay: Used for tapdelay register available in qspi
284 * zynqmp_qspi_set_tapdelay: To configure qspi tap delays
337 * The default settings of the QSPI controller's configurable parameters on
351 * - Enable the QSPI controller
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| /linux-6.15/Documentation/devicetree/bindings/spi/ |
| D | cdns,qspi-nor.yaml | 4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#
26 const: starfive,jh7110-qspi
37 enum: [ qspi, qspi-ocp, rstc_ref ]
48 enum: [ qspi, qspi-ocp ]
53 const: amd,pensando-elba-qspi
70 - amd,pensando-elba-qspi
72 - intel,lgm-qspi
73 - intel,socfpga-qspi
75 - starfive,jh7110-qspi
77 - ti,k2g-qspi
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| D | fsl,spi-fsl-qspi.yaml | 4 $id: http://devicetree.org/schemas/spi/fsl,spi-fsl-qspi.yaml#
19 - fsl,vf610-qspi
20 - fsl,imx6sx-qspi
21 - fsl,imx7d-qspi
22 - fsl,imx6ul-qspi
23 - fsl,ls1021a-qspi
24 - fsl,ls2080a-qspi
27 - fsl,ls1043a-qspi
28 - const: fsl,ls1021a-qspi
31 - fsl,imx8mq-qspi
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| D | renesas,rspi.yaml | 7 title: Renesas (Quad) Serial Peripheral Interface (RSPI/QSPI)
31 - renesas,qspi-r8a7742 # RZ/G1H
32 - renesas,qspi-r8a7743 # RZ/G1M
33 - renesas,qspi-r8a7744 # RZ/G1N
34 - renesas,qspi-r8a7745 # RZ/G1E
35 - renesas,qspi-r8a77470 # RZ/G1C
36 - renesas,qspi-r8a7790 # R-Car H2
37 - renesas,qspi-r8a7791 # R-Car M2-W
38 - renesas,qspi-r8a7792 # R-Car V2H
39 - renesas,qspi-r8a7793 # R-Car M2-N
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| D | qcom,spi-qcom-qspi.yaml | 4 $id: http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#
7 title: Qualcomm Quad Serial Peripheral Interface (QSPI)
12 description: The QSPI controller allows SPI protocol communication in single,
23 - qcom,sc7180-qspi
24 - qcom,sc7280-qspi
25 - qcom,sdm845-qspi
27 - const: qcom,qspi-v1
46 - description: QSPI core clock
55 - const: qspi-config
56 - const: qspi-memory
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| D | brcm,spi-bcm-qspi.yaml | 4 $id: http://devicetree.org/schemas/spi/brcm,spi-bcm-qspi.yaml#
36 - brcm,spi-bcm7425-qspi
37 - brcm,spi-bcm7429-qspi
38 - brcm,spi-bcm7435-qspi
39 - brcm,spi-bcm7445-qspi
40 - brcm,spi-bcm7216-qspi
41 - brcm,spi-bcm7278-qspi
42 - const: brcm,spi-bcm-qspi
47 - brcm,spi-brcmstb-qspi
49 - brcm,spi-nsp-qspi
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| D | nvidia,tegra210-quad.yaml | 19 - nvidia,tegra210-qspi
20 - nvidia,tegra186-qspi
21 - nvidia,tegra194-qspi
22 - nvidia,tegra234-qspi
23 - nvidia,tegra241-qspi
33 - const: qspi
78 compatible = "nvidia,tegra210-qspi";
85 clock-names = "qspi", "qspi_out";
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| D | ti,qspi.yaml | 4 $id: http://devicetree.org/schemas/spi/ti,qspi.yaml#
7 title: TI QSPI controller
18 - ti,am4372-qspi
19 - ti,dra7xxx-qspi
48 Name of the hwmod associated to the QSPI. This is for legacy
55 Handle to system control region containing QSPI chipselect register
83 compatible = "ti,dra7xxx-qspi";
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| D | spi-zynqmp-qspi.yaml | 4 $id: http://devicetree.org/schemas/spi/spi-zynqmp-qspi.yaml#
15 - xlnx,versal-qspi-1.0
16 - xlnx,zynqmp-qspi-1.0
55 const: xlnx,zynqmp-qspi-1.0
72 qspi: spi@ff0f0000 {
73 compatible = "xlnx,zynqmp-qspi-1.0";
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| D | st,stm32-qspi.yaml | 4 $id: http://devicetree.org/schemas/spi/st,stm32-qspi.yaml#
7 title: STMicroelectronics STM32 Quad Serial Peripheral Interface (QSPI)
18 const: st,stm32f469-qspi
27 - const: qspi
68 compatible = "st,stm32f469-qspi";
70 reg-names = "qspi", "qspi_mm";
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| D | xlnx,zynq-qspi.yaml | 4 $id: http://devicetree.org/schemas/spi/xlnx,zynq-qspi.yaml#
7 title: Xilinx Zynq QSPI controller
10 The Xilinx Zynq QSPI controller is used to access multi-bit serial flash
22 const: xlnx,zynq-qspi-1.0
52 compatible = "xlnx,zynq-qspi-1.0";
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| D | atmel,quadspi.yaml | 7 title: Atmel Quad Serial Peripheral Interface (QSPI)
18 - atmel,sama5d2-qspi
19 - microchip,sam9x60-qspi
20 - microchip,sama7g5-qspi
81 compatible = "atmel,sama5d2-qspi";
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| /linux-6.15/arch/m68k/include/asm/ |
| D | mcfqspi.h | 3 * Definitions for Freescale Coldfire QSPI module
12 * struct mcfqspi_cs_control - chip select control for the coldfire qspi driver
18 * The QSPI module has 4 hardware chip selects. We don't use them. Instead
20 * platform data for each QSPI master controller. Only the select and
31 * struct mcfqspi_platform_data - platform data for the coldfire qspi driver
32 * @bus_num: board specific identifier for this qspi driver.
33 * @num_chipselects: number of chip selects supported by this qspi driver.
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| /linux-6.15/arch/arm/boot/dts/xilinx/ |
| D | zynq-cc108.dts | 21 spi0 = &qspi;
55 &qspi {
67 label = "qspi-fsbl-uboot-bs";
71 label = "qspi-linux";
75 label = "qspi-rootfs";
79 label = "qspi-devicetree";
83 label = "qspi-scratch";
87 label = "qspi-uboot-env";
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| D | zynq-zed.dts | 16 spi0 = &qspi;
50 &qspi {
66 label = "qspi-fsbl-uboot";
70 label = "qspi-linux";
74 label = "qspi-device-tree";
78 label = "qspi-rootfs";
82 label = "qspi-bitstream";
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| D | zynq-zc770-xm013.dts | 18 spi0 = &qspi;
61 &qspi {
76 label = "qspi-fsbl-uboot";
80 label = "qspi-linux";
84 label = "qspi-device-tree";
88 label = "qspi-rootfs";
92 label = "qspi-bitstream";
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| D | zynq-zc770-xm010.dts | 18 spi0 = &qspi;
62 &qspi {
76 label = "qspi-fsbl-uboot";
80 label = "qspi-linux";
84 label = "qspi-device-tree";
88 label = "qspi-rootfs";
92 label = "qspi-bitstream";
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| /linux-6.15/arch/arm/boot/dts/ti/omap/ |
| D | dra7-evm-common.dtsi | 134 &qspi {
153 label = "QSPI.SPL";
157 label = "QSPI.SPL.backup1";
161 label = "QSPI.SPL.backup2";
165 label = "QSPI.SPL.backup3";
169 label = "QSPI.u-boot";
173 label = "QSPI.u-boot-spl-os";
177 label = "QSPI.u-boot-env";
181 label = "QSPI.u-boot-env.backup1";
185 label = "QSPI.kernel";
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| /linux-6.15/arch/arm/boot/dts/renesas/ |
| D | r8a7742-iwg21m.dtsi | 39 /* GP0_18 set low to select QSPI. Doing so will disable VIN2 */
40 qspi-en-hog {
83 qspi_pins: qspi {
85 function = "qspi";
89 &qspi {
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