1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Cadence Quad/Octal SPI controller
8
9maintainers:
10  - Vaishnav Achath <vaishnav.a@ti.com>
11
12allOf:
13  - $ref: spi-controller.yaml#
14  - if:
15      properties:
16        compatible:
17          contains:
18            const: xlnx,versal-ospi-1.0
19    then:
20      required:
21        - power-domains
22  - if:
23      properties:
24        compatible:
25          contains:
26            const: starfive,jh7110-qspi
27    then:
28      properties:
29        resets:
30          minItems: 2
31          maxItems: 3
32
33        reset-names:
34          minItems: 2
35          maxItems: 3
36          items:
37            enum: [ qspi, qspi-ocp, rstc_ref ]
38
39    else:
40      properties:
41        resets:
42          maxItems: 2
43
44        reset-names:
45          minItems: 1
46          maxItems: 2
47          items:
48            enum: [ qspi, qspi-ocp ]
49  - if:
50      properties:
51        compatible:
52          contains:
53            const: amd,pensando-elba-qspi
54    then:
55      properties:
56        cdns,fifo-depth:
57          enum: [ 128, 256, 1024 ]
58          default: 1024
59    else:
60      properties:
61        cdns,fifo-depth:
62          enum: [ 128, 256 ]
63          default: 128
64
65properties:
66  compatible:
67    oneOf:
68      - items:
69          - enum:
70              - amd,pensando-elba-qspi
71              - amd,versal2-ospi
72              - intel,lgm-qspi
73              - intel,socfpga-qspi
74              - mobileye,eyeq5-ospi
75              - starfive,jh7110-qspi
76              - ti,am654-ospi
77              - ti,k2g-qspi
78              - xlnx,versal-ospi-1.0
79          # The compatible is qspi-nor for historical reasons but such
80          # controllers are meant to be used with flashes of all kinds,
81          # ie. also NAND flashes, not only NOR flashes.
82          - const: cdns,qspi-nor
83      - const: cdns,qspi-nor
84        deprecated: true
85
86  reg:
87    items:
88      - description: the controller register set
89      - description: the controller data area
90
91  interrupts:
92    maxItems: 1
93
94  clocks:
95    minItems: 1
96    maxItems: 3
97
98  clock-names:
99    oneOf:
100      - items:
101          - const: ref
102      - items:
103          - const: ref
104          - const: ahb
105          - const: apb
106
107  cdns,fifo-depth:
108    description:
109      Size of the data FIFO in words.
110    $ref: /schemas/types.yaml#/definitions/uint32
111
112  cdns,fifo-width:
113    $ref: /schemas/types.yaml#/definitions/uint32
114    description:
115      Bus width of the data FIFO in bytes.
116    default: 4
117
118  cdns,trigger-address:
119    $ref: /schemas/types.yaml#/definitions/uint32
120    description:
121      32-bit indirect AHB trigger address.
122
123  cdns,is-decoded-cs:
124    type: boolean
125    description:
126      Flag to indicate whether decoder is used to select different chip select
127      for different memory regions.
128
129  cdns,rclk-en:
130    type: boolean
131    description:
132      Flag to indicate that QSPI return clock is used to latch the read
133      data rather than the QSPI clock. Make sure that QSPI return clock
134      is populated on the board before using this property.
135
136  power-domains:
137    maxItems: 1
138
139  resets:
140    minItems: 2
141    maxItems: 3
142
143  reset-names:
144    minItems: 2
145    maxItems: 3
146    items:
147      enum: [ qspi, qspi-ocp, rstc_ref ]
148
149patternProperties:
150  "^flash@[0-9a-f]+$":
151    type: object
152    $ref: cdns,qspi-nor-peripheral-props.yaml
153    additionalProperties: true
154    required:
155      - cdns,read-delay
156      - cdns,tshsl-ns
157      - cdns,tsd2d-ns
158      - cdns,tchsh-ns
159      - cdns,tslch-ns
160
161required:
162  - compatible
163  - reg
164  - interrupts
165  - clocks
166  - cdns,fifo-width
167  - cdns,trigger-address
168  - '#address-cells'
169  - '#size-cells'
170
171unevaluatedProperties: false
172
173examples:
174  - |
175    qspi: spi@ff705000 {
176        compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
177        #address-cells = <1>;
178        #size-cells = <0>;
179        reg = <0xff705000 0x1000>,
180              <0xffa00000 0x1000>;
181        interrupts = <0 151 4>;
182        clocks = <&qspi_clk>;
183        cdns,fifo-depth = <128>;
184        cdns,fifo-width = <4>;
185        cdns,trigger-address = <0x00000000>;
186        resets = <&rst 0x1>, <&rst 0x2>;
187        reset-names = "qspi", "qspi-ocp";
188
189        flash@0 {
190            compatible = "jedec,spi-nor";
191            reg = <0x0>;
192            cdns,read-delay = <4>;
193            cdns,tshsl-ns = <60>;
194            cdns,tsd2d-ns = <60>;
195            cdns,tchsh-ns = <60>;
196            cdns,tslch-ns = <60>;
197        };
198    };
199