1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
6 #include <linux/bitfield.h>
7 #include <linux/clk.h>
8 #include <linux/dmaengine.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/errno.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/io.h>
13 #include <linux/iopoll.h>
14 #include <linux/interrupt.h>
15 #include <linux/module.h>
16 #include <linux/mutex.h>
17 #include <linux/of.h>
18 #include <linux/pinctrl/consumer.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/platform_device.h>
21 #include <linux/reset.h>
22 #include <linux/sizes.h>
23 #include <linux/spi/spi-mem.h>
24
25 #define QSPI_CR 0x00
26 #define CR_EN BIT(0)
27 #define CR_ABORT BIT(1)
28 #define CR_DMAEN BIT(2)
29 #define CR_TCEN BIT(3)
30 #define CR_SSHIFT BIT(4)
31 #define CR_DFM BIT(6)
32 #define CR_FSEL BIT(7)
33 #define CR_FTHRES_SHIFT 8
34 #define CR_TEIE BIT(16)
35 #define CR_TCIE BIT(17)
36 #define CR_FTIE BIT(18)
37 #define CR_SMIE BIT(19)
38 #define CR_TOIE BIT(20)
39 #define CR_APMS BIT(22)
40 #define CR_PRESC_MASK GENMASK(31, 24)
41
42 #define QSPI_DCR 0x04
43 #define DCR_FSIZE_MASK GENMASK(20, 16)
44
45 #define QSPI_SR 0x08
46 #define SR_TEF BIT(0)
47 #define SR_TCF BIT(1)
48 #define SR_FTF BIT(2)
49 #define SR_SMF BIT(3)
50 #define SR_TOF BIT(4)
51 #define SR_BUSY BIT(5)
52 #define SR_FLEVEL_MASK GENMASK(13, 8)
53
54 #define QSPI_FCR 0x0c
55 #define FCR_CTEF BIT(0)
56 #define FCR_CTCF BIT(1)
57 #define FCR_CSMF BIT(3)
58
59 #define QSPI_DLR 0x10
60
61 #define QSPI_CCR 0x14
62 #define CCR_INST_MASK GENMASK(7, 0)
63 #define CCR_IMODE_MASK GENMASK(9, 8)
64 #define CCR_ADMODE_MASK GENMASK(11, 10)
65 #define CCR_ADSIZE_MASK GENMASK(13, 12)
66 #define CCR_DCYC_MASK GENMASK(22, 18)
67 #define CCR_DMODE_MASK GENMASK(25, 24)
68 #define CCR_FMODE_MASK GENMASK(27, 26)
69 #define CCR_FMODE_INDW (0U << 26)
70 #define CCR_FMODE_INDR (1U << 26)
71 #define CCR_FMODE_APM (2U << 26)
72 #define CCR_FMODE_MM (3U << 26)
73 #define CCR_BUSWIDTH_0 0x0
74 #define CCR_BUSWIDTH_1 0x1
75 #define CCR_BUSWIDTH_2 0x2
76 #define CCR_BUSWIDTH_4 0x3
77
78 #define QSPI_AR 0x18
79 #define QSPI_ABR 0x1c
80 #define QSPI_DR 0x20
81 #define QSPI_PSMKR 0x24
82 #define QSPI_PSMAR 0x28
83 #define QSPI_PIR 0x2c
84 #define QSPI_LPTR 0x30
85
86 #define STM32_QSPI_MAX_MMAP_SZ SZ_256M
87 #define STM32_QSPI_MAX_NORCHIP 2
88
89 #define STM32_FIFO_TIMEOUT_US 30000
90 #define STM32_BUSY_TIMEOUT_US 100000
91 #define STM32_ABT_TIMEOUT_US 100000
92 #define STM32_COMP_TIMEOUT_MS 1000
93 #define STM32_AUTOSUSPEND_DELAY -1
94
95 struct stm32_qspi_flash {
96 u32 cs;
97 u32 presc;
98 };
99
100 struct stm32_qspi {
101 struct device *dev;
102 struct spi_controller *ctrl;
103 phys_addr_t phys_base;
104 void __iomem *io_base;
105 void __iomem *mm_base;
106 resource_size_t mm_size;
107 struct clk *clk;
108 u32 clk_rate;
109 struct stm32_qspi_flash flash[STM32_QSPI_MAX_NORCHIP];
110 struct completion data_completion;
111 struct completion match_completion;
112 u32 fmode;
113
114 struct dma_chan *dma_chtx;
115 struct dma_chan *dma_chrx;
116 struct completion dma_completion;
117
118 u32 cr_reg;
119 u32 dcr_reg;
120 unsigned long status_timeout;
121
122 /*
123 * to protect device configuration, could be different between
124 * 2 flash access (bk1, bk2)
125 */
126 struct mutex lock;
127 };
128
stm32_qspi_irq(int irq,void * dev_id)129 static irqreturn_t stm32_qspi_irq(int irq, void *dev_id)
130 {
131 struct stm32_qspi *qspi = (struct stm32_qspi *)dev_id;
132 u32 cr, sr;
133
134 cr = readl_relaxed(qspi->io_base + QSPI_CR);
135 sr = readl_relaxed(qspi->io_base + QSPI_SR);
136
137 if (cr & CR_SMIE && sr & SR_SMF) {
138 /* disable irq */
139 cr &= ~CR_SMIE;
140 writel_relaxed(cr, qspi->io_base + QSPI_CR);
141 complete(&qspi->match_completion);
142
143 return IRQ_HANDLED;
144 }
145
146 if (sr & (SR_TEF | SR_TCF)) {
147 /* disable irq */
148 cr &= ~CR_TCIE & ~CR_TEIE;
149 writel_relaxed(cr, qspi->io_base + QSPI_CR);
150 complete(&qspi->data_completion);
151 }
152
153 return IRQ_HANDLED;
154 }
155
stm32_qspi_read_fifo(u8 * val,void __iomem * addr)156 static void stm32_qspi_read_fifo(u8 *val, void __iomem *addr)
157 {
158 *val = readb_relaxed(addr);
159 }
160
stm32_qspi_write_fifo(u8 * val,void __iomem * addr)161 static void stm32_qspi_write_fifo(u8 *val, void __iomem *addr)
162 {
163 writeb_relaxed(*val, addr);
164 }
165
stm32_qspi_tx_poll(struct stm32_qspi * qspi,const struct spi_mem_op * op)166 static int stm32_qspi_tx_poll(struct stm32_qspi *qspi,
167 const struct spi_mem_op *op)
168 {
169 void (*tx_fifo)(u8 *val, void __iomem *addr);
170 u32 len = op->data.nbytes, sr;
171 u8 *buf;
172 int ret;
173
174 if (op->data.dir == SPI_MEM_DATA_IN) {
175 tx_fifo = stm32_qspi_read_fifo;
176 buf = op->data.buf.in;
177
178 } else {
179 tx_fifo = stm32_qspi_write_fifo;
180 buf = (u8 *)op->data.buf.out;
181 }
182
183 while (len--) {
184 ret = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR,
185 sr, (sr & SR_FTF), 1,
186 STM32_FIFO_TIMEOUT_US);
187 if (ret) {
188 dev_err(qspi->dev, "fifo timeout (len:%d stat:%#x)\n",
189 len, sr);
190 return ret;
191 }
192 tx_fifo(buf++, qspi->io_base + QSPI_DR);
193 }
194
195 return 0;
196 }
197
stm32_qspi_tx_mm(struct stm32_qspi * qspi,const struct spi_mem_op * op)198 static int stm32_qspi_tx_mm(struct stm32_qspi *qspi,
199 const struct spi_mem_op *op)
200 {
201 memcpy_fromio(op->data.buf.in, qspi->mm_base + op->addr.val,
202 op->data.nbytes);
203 return 0;
204 }
205
stm32_qspi_dma_callback(void * arg)206 static void stm32_qspi_dma_callback(void *arg)
207 {
208 struct completion *dma_completion = arg;
209
210 complete(dma_completion);
211 }
212
stm32_qspi_tx_dma(struct stm32_qspi * qspi,const struct spi_mem_op * op)213 static int stm32_qspi_tx_dma(struct stm32_qspi *qspi,
214 const struct spi_mem_op *op)
215 {
216 struct dma_async_tx_descriptor *desc;
217 enum dma_transfer_direction dma_dir;
218 struct dma_chan *dma_ch;
219 struct sg_table sgt;
220 dma_cookie_t cookie;
221 u32 cr, t_out;
222 int err;
223
224 if (op->data.dir == SPI_MEM_DATA_IN) {
225 dma_dir = DMA_DEV_TO_MEM;
226 dma_ch = qspi->dma_chrx;
227 } else {
228 dma_dir = DMA_MEM_TO_DEV;
229 dma_ch = qspi->dma_chtx;
230 }
231
232 /*
233 * spi_map_buf return -EINVAL if the buffer is not DMA-able
234 * (DMA-able: in vmalloc | kmap | virt_addr_valid)
235 */
236 err = spi_controller_dma_map_mem_op_data(qspi->ctrl, op, &sgt);
237 if (err)
238 return err;
239
240 desc = dmaengine_prep_slave_sg(dma_ch, sgt.sgl, sgt.nents,
241 dma_dir, DMA_PREP_INTERRUPT);
242 if (!desc) {
243 err = -ENOMEM;
244 goto out_unmap;
245 }
246
247 cr = readl_relaxed(qspi->io_base + QSPI_CR);
248
249 reinit_completion(&qspi->dma_completion);
250 desc->callback = stm32_qspi_dma_callback;
251 desc->callback_param = &qspi->dma_completion;
252 cookie = dmaengine_submit(desc);
253 err = dma_submit_error(cookie);
254 if (err)
255 goto out;
256
257 dma_async_issue_pending(dma_ch);
258
259 writel_relaxed(cr | CR_DMAEN, qspi->io_base + QSPI_CR);
260
261 t_out = sgt.nents * STM32_COMP_TIMEOUT_MS;
262 if (!wait_for_completion_timeout(&qspi->dma_completion,
263 msecs_to_jiffies(t_out)))
264 err = -ETIMEDOUT;
265
266 if (err)
267 dmaengine_terminate_all(dma_ch);
268
269 out:
270 writel_relaxed(cr & ~CR_DMAEN, qspi->io_base + QSPI_CR);
271 out_unmap:
272 spi_controller_dma_unmap_mem_op_data(qspi->ctrl, op, &sgt);
273
274 return err;
275 }
276
stm32_qspi_tx(struct stm32_qspi * qspi,const struct spi_mem_op * op)277 static int stm32_qspi_tx(struct stm32_qspi *qspi, const struct spi_mem_op *op)
278 {
279 if (!op->data.nbytes)
280 return 0;
281
282 if (qspi->fmode == CCR_FMODE_MM)
283 return stm32_qspi_tx_mm(qspi, op);
284 else if (((op->data.dir == SPI_MEM_DATA_IN && qspi->dma_chrx) ||
285 (op->data.dir == SPI_MEM_DATA_OUT && qspi->dma_chtx)) &&
286 op->data.nbytes > 4)
287 if (!stm32_qspi_tx_dma(qspi, op))
288 return 0;
289
290 return stm32_qspi_tx_poll(qspi, op);
291 }
292
stm32_qspi_wait_nobusy(struct stm32_qspi * qspi)293 static int stm32_qspi_wait_nobusy(struct stm32_qspi *qspi)
294 {
295 u32 sr;
296
297 return readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, sr,
298 !(sr & SR_BUSY), 1,
299 STM32_BUSY_TIMEOUT_US);
300 }
301
stm32_qspi_wait_cmd(struct stm32_qspi * qspi)302 static int stm32_qspi_wait_cmd(struct stm32_qspi *qspi)
303 {
304 u32 cr, sr;
305 int err = 0;
306
307 if ((readl_relaxed(qspi->io_base + QSPI_SR) & SR_TCF) ||
308 qspi->fmode == CCR_FMODE_APM)
309 goto out;
310
311 reinit_completion(&qspi->data_completion);
312 cr = readl_relaxed(qspi->io_base + QSPI_CR);
313 writel_relaxed(cr | CR_TCIE | CR_TEIE, qspi->io_base + QSPI_CR);
314
315 if (!wait_for_completion_timeout(&qspi->data_completion,
316 msecs_to_jiffies(STM32_COMP_TIMEOUT_MS))) {
317 err = -ETIMEDOUT;
318 } else {
319 sr = readl_relaxed(qspi->io_base + QSPI_SR);
320 if (sr & SR_TEF)
321 err = -EIO;
322 }
323
324 out:
325 /* clear flags */
326 writel_relaxed(FCR_CTCF | FCR_CTEF, qspi->io_base + QSPI_FCR);
327 if (!err)
328 err = stm32_qspi_wait_nobusy(qspi);
329
330 return err;
331 }
332
stm32_qspi_wait_poll_status(struct stm32_qspi * qspi)333 static int stm32_qspi_wait_poll_status(struct stm32_qspi *qspi)
334 {
335 u32 cr;
336
337 reinit_completion(&qspi->match_completion);
338 cr = readl_relaxed(qspi->io_base + QSPI_CR);
339 writel_relaxed(cr | CR_SMIE, qspi->io_base + QSPI_CR);
340
341 if (!wait_for_completion_timeout(&qspi->match_completion,
342 msecs_to_jiffies(qspi->status_timeout)))
343 return -ETIMEDOUT;
344
345 writel_relaxed(FCR_CSMF, qspi->io_base + QSPI_FCR);
346
347 return 0;
348 }
349
stm32_qspi_get_mode(u8 buswidth)350 static int stm32_qspi_get_mode(u8 buswidth)
351 {
352 if (buswidth >= 4)
353 return CCR_BUSWIDTH_4;
354
355 return buswidth;
356 }
357
stm32_qspi_send(struct spi_device * spi,const struct spi_mem_op * op)358 static int stm32_qspi_send(struct spi_device *spi, const struct spi_mem_op *op)
359 {
360 struct stm32_qspi *qspi = spi_controller_get_devdata(spi->controller);
361 struct stm32_qspi_flash *flash = &qspi->flash[spi_get_chipselect(spi, 0)];
362 u32 ccr, cr;
363 int timeout, err = 0, err_poll_status = 0;
364
365 cr = readl_relaxed(qspi->io_base + QSPI_CR);
366 cr &= ~CR_PRESC_MASK & ~CR_FSEL;
367 cr |= FIELD_PREP(CR_PRESC_MASK, flash->presc);
368 cr |= FIELD_PREP(CR_FSEL, flash->cs);
369 writel_relaxed(cr, qspi->io_base + QSPI_CR);
370
371 if (op->data.nbytes)
372 writel_relaxed(op->data.nbytes - 1,
373 qspi->io_base + QSPI_DLR);
374
375 ccr = qspi->fmode;
376 ccr |= FIELD_PREP(CCR_INST_MASK, op->cmd.opcode);
377 ccr |= FIELD_PREP(CCR_IMODE_MASK,
378 stm32_qspi_get_mode(op->cmd.buswidth));
379
380 if (op->addr.nbytes) {
381 ccr |= FIELD_PREP(CCR_ADMODE_MASK,
382 stm32_qspi_get_mode(op->addr.buswidth));
383 ccr |= FIELD_PREP(CCR_ADSIZE_MASK, op->addr.nbytes - 1);
384 }
385
386 if (op->dummy.nbytes)
387 ccr |= FIELD_PREP(CCR_DCYC_MASK,
388 op->dummy.nbytes * 8 / op->dummy.buswidth);
389
390 if (op->data.nbytes) {
391 ccr |= FIELD_PREP(CCR_DMODE_MASK,
392 stm32_qspi_get_mode(op->data.buswidth));
393 }
394
395 writel_relaxed(ccr, qspi->io_base + QSPI_CCR);
396
397 if (op->addr.nbytes && qspi->fmode != CCR_FMODE_MM)
398 writel_relaxed(op->addr.val, qspi->io_base + QSPI_AR);
399
400 if (qspi->fmode == CCR_FMODE_APM)
401 err_poll_status = stm32_qspi_wait_poll_status(qspi);
402
403 err = stm32_qspi_tx(qspi, op);
404
405 /*
406 * Abort in:
407 * -error case
408 * -read memory map: prefetching must be stopped if we read the last
409 * byte of device (device size - fifo size). like device size is not
410 * knows, the prefetching is always stop.
411 */
412 if (err || err_poll_status || qspi->fmode == CCR_FMODE_MM)
413 goto abort;
414
415 /* wait end of tx in indirect mode */
416 err = stm32_qspi_wait_cmd(qspi);
417 if (err)
418 goto abort;
419
420 return 0;
421
422 abort:
423 cr = readl_relaxed(qspi->io_base + QSPI_CR) | CR_ABORT;
424 writel_relaxed(cr, qspi->io_base + QSPI_CR);
425
426 /* wait clear of abort bit by hw */
427 timeout = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_CR,
428 cr, !(cr & CR_ABORT), 1,
429 STM32_ABT_TIMEOUT_US);
430
431 writel_relaxed(FCR_CTCF | FCR_CSMF, qspi->io_base + QSPI_FCR);
432
433 if (err || err_poll_status || timeout)
434 dev_err(qspi->dev, "%s err:%d err_poll_status:%d abort timeout:%d\n",
435 __func__, err, err_poll_status, timeout);
436
437 return err;
438 }
439
stm32_qspi_poll_status(struct spi_mem * mem,const struct spi_mem_op * op,u16 mask,u16 match,unsigned long initial_delay_us,unsigned long polling_rate_us,unsigned long timeout_ms)440 static int stm32_qspi_poll_status(struct spi_mem *mem, const struct spi_mem_op *op,
441 u16 mask, u16 match,
442 unsigned long initial_delay_us,
443 unsigned long polling_rate_us,
444 unsigned long timeout_ms)
445 {
446 struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->controller);
447 int ret;
448
449 if (!spi_mem_supports_op(mem, op))
450 return -EOPNOTSUPP;
451
452 ret = pm_runtime_resume_and_get(qspi->dev);
453 if (ret < 0)
454 return ret;
455
456 mutex_lock(&qspi->lock);
457
458 writel_relaxed(mask, qspi->io_base + QSPI_PSMKR);
459 writel_relaxed(match, qspi->io_base + QSPI_PSMAR);
460 qspi->fmode = CCR_FMODE_APM;
461 qspi->status_timeout = timeout_ms;
462
463 ret = stm32_qspi_send(mem->spi, op);
464 mutex_unlock(&qspi->lock);
465
466 pm_runtime_mark_last_busy(qspi->dev);
467 pm_runtime_put_autosuspend(qspi->dev);
468
469 return ret;
470 }
471
stm32_qspi_exec_op(struct spi_mem * mem,const struct spi_mem_op * op)472 static int stm32_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
473 {
474 struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->controller);
475 int ret;
476
477 ret = pm_runtime_resume_and_get(qspi->dev);
478 if (ret < 0)
479 return ret;
480
481 mutex_lock(&qspi->lock);
482 if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes)
483 qspi->fmode = CCR_FMODE_INDR;
484 else
485 qspi->fmode = CCR_FMODE_INDW;
486
487 ret = stm32_qspi_send(mem->spi, op);
488 mutex_unlock(&qspi->lock);
489
490 pm_runtime_mark_last_busy(qspi->dev);
491 pm_runtime_put_autosuspend(qspi->dev);
492
493 return ret;
494 }
495
stm32_qspi_dirmap_create(struct spi_mem_dirmap_desc * desc)496 static int stm32_qspi_dirmap_create(struct spi_mem_dirmap_desc *desc)
497 {
498 struct stm32_qspi *qspi = spi_controller_get_devdata(desc->mem->spi->controller);
499
500 if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_OUT)
501 return -EOPNOTSUPP;
502
503 /* should never happen, as mm_base == null is an error probe exit condition */
504 if (!qspi->mm_base && desc->info.op_tmpl.data.dir == SPI_MEM_DATA_IN)
505 return -EOPNOTSUPP;
506
507 if (!qspi->mm_size)
508 return -EOPNOTSUPP;
509
510 return 0;
511 }
512
stm32_qspi_dirmap_read(struct spi_mem_dirmap_desc * desc,u64 offs,size_t len,void * buf)513 static ssize_t stm32_qspi_dirmap_read(struct spi_mem_dirmap_desc *desc,
514 u64 offs, size_t len, void *buf)
515 {
516 struct stm32_qspi *qspi = spi_controller_get_devdata(desc->mem->spi->controller);
517 struct spi_mem_op op;
518 u32 addr_max;
519 int ret;
520
521 ret = pm_runtime_resume_and_get(qspi->dev);
522 if (ret < 0)
523 return ret;
524
525 mutex_lock(&qspi->lock);
526 /* make a local copy of desc op_tmpl and complete dirmap rdesc
527 * spi_mem_op template with offs, len and *buf in order to get
528 * all needed transfer information into struct spi_mem_op
529 */
530 memcpy(&op, &desc->info.op_tmpl, sizeof(struct spi_mem_op));
531 dev_dbg(qspi->dev, "%s len = 0x%zx offs = 0x%llx buf = 0x%p\n", __func__, len, offs, buf);
532
533 op.data.nbytes = len;
534 op.addr.val = desc->info.offset + offs;
535 op.data.buf.in = buf;
536
537 addr_max = op.addr.val + op.data.nbytes + 1;
538 if (addr_max < qspi->mm_size && op.addr.buswidth)
539 qspi->fmode = CCR_FMODE_MM;
540 else
541 qspi->fmode = CCR_FMODE_INDR;
542
543 ret = stm32_qspi_send(desc->mem->spi, &op);
544 mutex_unlock(&qspi->lock);
545
546 pm_runtime_mark_last_busy(qspi->dev);
547 pm_runtime_put_autosuspend(qspi->dev);
548
549 return ret ?: len;
550 }
551
stm32_qspi_transfer_one_message(struct spi_controller * ctrl,struct spi_message * msg)552 static int stm32_qspi_transfer_one_message(struct spi_controller *ctrl,
553 struct spi_message *msg)
554 {
555 struct stm32_qspi *qspi = spi_controller_get_devdata(ctrl);
556 struct spi_transfer *transfer;
557 struct spi_device *spi = msg->spi;
558 struct spi_mem_op op;
559 int ret = 0;
560
561 if (!spi_get_csgpiod(spi, 0))
562 return -EOPNOTSUPP;
563
564 ret = pm_runtime_resume_and_get(qspi->dev);
565 if (ret < 0)
566 return ret;
567
568 mutex_lock(&qspi->lock);
569
570 gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), true);
571
572 list_for_each_entry(transfer, &msg->transfers, transfer_list) {
573 u8 dummy_bytes = 0;
574
575 memset(&op, 0, sizeof(op));
576
577 dev_dbg(qspi->dev, "tx_buf:%p tx_nbits:%d rx_buf:%p rx_nbits:%d len:%d dummy_data:%d\n",
578 transfer->tx_buf, transfer->tx_nbits,
579 transfer->rx_buf, transfer->rx_nbits,
580 transfer->len, transfer->dummy_data);
581
582 /*
583 * QSPI hardware supports dummy bytes transfer.
584 * If current transfer is dummy byte, merge it with the next
585 * transfer in order to take into account QSPI block constraint
586 */
587 if (transfer->dummy_data) {
588 op.dummy.buswidth = transfer->tx_nbits;
589 op.dummy.nbytes = transfer->len;
590 dummy_bytes = transfer->len;
591
592 /* if happens, means that message is not correctly built */
593 if (list_is_last(&transfer->transfer_list, &msg->transfers)) {
594 ret = -EINVAL;
595 goto end_of_transfer;
596 }
597
598 transfer = list_next_entry(transfer, transfer_list);
599 }
600
601 op.data.nbytes = transfer->len;
602
603 if (transfer->rx_buf) {
604 qspi->fmode = CCR_FMODE_INDR;
605 op.data.buswidth = transfer->rx_nbits;
606 op.data.dir = SPI_MEM_DATA_IN;
607 op.data.buf.in = transfer->rx_buf;
608 } else {
609 qspi->fmode = CCR_FMODE_INDW;
610 op.data.buswidth = transfer->tx_nbits;
611 op.data.dir = SPI_MEM_DATA_OUT;
612 op.data.buf.out = transfer->tx_buf;
613 }
614
615 ret = stm32_qspi_send(spi, &op);
616 if (ret)
617 goto end_of_transfer;
618
619 msg->actual_length += transfer->len + dummy_bytes;
620 }
621
622 end_of_transfer:
623 gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), false);
624
625 mutex_unlock(&qspi->lock);
626
627 msg->status = ret;
628 spi_finalize_current_message(ctrl);
629
630 pm_runtime_mark_last_busy(qspi->dev);
631 pm_runtime_put_autosuspend(qspi->dev);
632
633 return ret;
634 }
635
stm32_qspi_setup(struct spi_device * spi)636 static int stm32_qspi_setup(struct spi_device *spi)
637 {
638 struct spi_controller *ctrl = spi->controller;
639 struct stm32_qspi *qspi = spi_controller_get_devdata(ctrl);
640 struct stm32_qspi_flash *flash;
641 u32 presc, mode;
642 int ret;
643
644 if (ctrl->busy)
645 return -EBUSY;
646
647 if (!spi->max_speed_hz)
648 return -EINVAL;
649
650 mode = spi->mode & (SPI_TX_OCTAL | SPI_RX_OCTAL);
651 if (mode && gpiod_count(qspi->dev, "cs") == -ENOENT) {
652 dev_err(qspi->dev, "spi-rx-bus-width\\/spi-tx-bus-width\\/cs-gpios\n");
653 dev_err(qspi->dev, "configuration not supported\n");
654
655 return -EINVAL;
656 }
657
658 ret = pm_runtime_resume_and_get(qspi->dev);
659 if (ret < 0)
660 return ret;
661
662 presc = DIV_ROUND_UP(qspi->clk_rate, spi->max_speed_hz) - 1;
663
664 flash = &qspi->flash[spi_get_chipselect(spi, 0)];
665 flash->cs = spi_get_chipselect(spi, 0);
666 flash->presc = presc;
667
668 mutex_lock(&qspi->lock);
669 qspi->cr_reg = CR_APMS | 3 << CR_FTHRES_SHIFT | CR_SSHIFT | CR_EN;
670
671 /*
672 * Dual flash mode is only enable in case SPI_TX_OCTAL or SPI_RX_OCTAL
673 * is set in spi->mode and "cs-gpios" properties is found in DT
674 */
675 if (mode) {
676 qspi->cr_reg |= CR_DFM;
677 dev_dbg(qspi->dev, "Dual flash mode enable");
678 }
679
680 writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR);
681
682 /* set dcr fsize to max address */
683 qspi->dcr_reg = DCR_FSIZE_MASK;
684 writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR);
685 mutex_unlock(&qspi->lock);
686
687 pm_runtime_mark_last_busy(qspi->dev);
688 pm_runtime_put_autosuspend(qspi->dev);
689
690 return 0;
691 }
692
stm32_qspi_dma_setup(struct stm32_qspi * qspi)693 static int stm32_qspi_dma_setup(struct stm32_qspi *qspi)
694 {
695 struct dma_slave_config dma_cfg;
696 struct device *dev = qspi->dev;
697 int ret = 0;
698
699 memset(&dma_cfg, 0, sizeof(dma_cfg));
700
701 dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
702 dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
703 dma_cfg.src_addr = qspi->phys_base + QSPI_DR;
704 dma_cfg.dst_addr = qspi->phys_base + QSPI_DR;
705 dma_cfg.src_maxburst = 4;
706 dma_cfg.dst_maxburst = 4;
707
708 qspi->dma_chrx = dma_request_chan(dev, "rx");
709 if (IS_ERR(qspi->dma_chrx)) {
710 ret = PTR_ERR(qspi->dma_chrx);
711 qspi->dma_chrx = NULL;
712 if (ret == -EPROBE_DEFER)
713 goto out;
714 } else {
715 if (dmaengine_slave_config(qspi->dma_chrx, &dma_cfg)) {
716 dev_err(dev, "dma rx config failed\n");
717 dma_release_channel(qspi->dma_chrx);
718 qspi->dma_chrx = NULL;
719 }
720 }
721
722 qspi->dma_chtx = dma_request_chan(dev, "tx");
723 if (IS_ERR(qspi->dma_chtx)) {
724 ret = PTR_ERR(qspi->dma_chtx);
725 qspi->dma_chtx = NULL;
726 } else {
727 if (dmaengine_slave_config(qspi->dma_chtx, &dma_cfg)) {
728 dev_err(dev, "dma tx config failed\n");
729 dma_release_channel(qspi->dma_chtx);
730 qspi->dma_chtx = NULL;
731 }
732 }
733
734 out:
735 init_completion(&qspi->dma_completion);
736
737 if (ret != -EPROBE_DEFER)
738 ret = 0;
739
740 return ret;
741 }
742
stm32_qspi_dma_free(struct stm32_qspi * qspi)743 static void stm32_qspi_dma_free(struct stm32_qspi *qspi)
744 {
745 if (qspi->dma_chtx)
746 dma_release_channel(qspi->dma_chtx);
747 if (qspi->dma_chrx)
748 dma_release_channel(qspi->dma_chrx);
749 }
750
751 /*
752 * no special host constraint, so use default spi_mem_default_supports_op
753 * to check supported mode.
754 */
755 static const struct spi_controller_mem_ops stm32_qspi_mem_ops = {
756 .exec_op = stm32_qspi_exec_op,
757 .dirmap_create = stm32_qspi_dirmap_create,
758 .dirmap_read = stm32_qspi_dirmap_read,
759 .poll_status = stm32_qspi_poll_status,
760 };
761
stm32_qspi_probe(struct platform_device * pdev)762 static int stm32_qspi_probe(struct platform_device *pdev)
763 {
764 struct device *dev = &pdev->dev;
765 struct spi_controller *ctrl;
766 struct reset_control *rstc;
767 struct stm32_qspi *qspi;
768 struct resource *res;
769 int ret, irq;
770
771 ctrl = devm_spi_alloc_host(dev, sizeof(*qspi));
772 if (!ctrl)
773 return -ENOMEM;
774
775 qspi = spi_controller_get_devdata(ctrl);
776 qspi->ctrl = ctrl;
777
778 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi");
779 qspi->io_base = devm_ioremap_resource(dev, res);
780 if (IS_ERR(qspi->io_base))
781 return PTR_ERR(qspi->io_base);
782
783 qspi->phys_base = res->start;
784
785 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mm");
786 qspi->mm_base = devm_ioremap_resource(dev, res);
787 if (IS_ERR(qspi->mm_base))
788 return PTR_ERR(qspi->mm_base);
789
790 qspi->mm_size = resource_size(res);
791 if (qspi->mm_size > STM32_QSPI_MAX_MMAP_SZ)
792 return -EINVAL;
793
794 irq = platform_get_irq(pdev, 0);
795 if (irq < 0)
796 return irq;
797
798 ret = devm_request_irq(dev, irq, stm32_qspi_irq, 0,
799 dev_name(dev), qspi);
800 if (ret) {
801 dev_err(dev, "failed to request irq\n");
802 return ret;
803 }
804
805 init_completion(&qspi->data_completion);
806 init_completion(&qspi->match_completion);
807
808 qspi->clk = devm_clk_get(dev, NULL);
809 if (IS_ERR(qspi->clk))
810 return PTR_ERR(qspi->clk);
811
812 qspi->clk_rate = clk_get_rate(qspi->clk);
813 if (!qspi->clk_rate)
814 return -EINVAL;
815
816 ret = clk_prepare_enable(qspi->clk);
817 if (ret) {
818 dev_err(dev, "can not enable the clock\n");
819 return ret;
820 }
821
822 rstc = devm_reset_control_get_exclusive(dev, NULL);
823 if (IS_ERR(rstc)) {
824 ret = PTR_ERR(rstc);
825 if (ret == -EPROBE_DEFER)
826 goto err_clk_disable;
827 } else {
828 reset_control_assert(rstc);
829 udelay(2);
830 reset_control_deassert(rstc);
831 }
832
833 qspi->dev = dev;
834 platform_set_drvdata(pdev, qspi);
835 ret = stm32_qspi_dma_setup(qspi);
836 if (ret)
837 goto err_dma_free;
838
839 mutex_init(&qspi->lock);
840
841 ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_OCTAL
842 | SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_OCTAL;
843 ctrl->setup = stm32_qspi_setup;
844 ctrl->bus_num = -1;
845 ctrl->mem_ops = &stm32_qspi_mem_ops;
846 ctrl->use_gpio_descriptors = true;
847 ctrl->transfer_one_message = stm32_qspi_transfer_one_message;
848 ctrl->num_chipselect = STM32_QSPI_MAX_NORCHIP;
849 ctrl->dev.of_node = dev->of_node;
850
851 pm_runtime_set_autosuspend_delay(dev, STM32_AUTOSUSPEND_DELAY);
852 pm_runtime_use_autosuspend(dev);
853 pm_runtime_set_active(dev);
854 pm_runtime_enable(dev);
855 pm_runtime_get_noresume(dev);
856
857 ret = spi_register_controller(ctrl);
858 if (ret)
859 goto err_pm_runtime_free;
860
861 pm_runtime_mark_last_busy(dev);
862 pm_runtime_put_autosuspend(dev);
863
864 return 0;
865
866 err_pm_runtime_free:
867 pm_runtime_get_sync(qspi->dev);
868 /* disable qspi */
869 writel_relaxed(0, qspi->io_base + QSPI_CR);
870 mutex_destroy(&qspi->lock);
871 pm_runtime_put_noidle(qspi->dev);
872 pm_runtime_disable(qspi->dev);
873 pm_runtime_set_suspended(qspi->dev);
874 pm_runtime_dont_use_autosuspend(qspi->dev);
875 err_dma_free:
876 stm32_qspi_dma_free(qspi);
877 err_clk_disable:
878 clk_disable_unprepare(qspi->clk);
879
880 return ret;
881 }
882
stm32_qspi_remove(struct platform_device * pdev)883 static void stm32_qspi_remove(struct platform_device *pdev)
884 {
885 struct stm32_qspi *qspi = platform_get_drvdata(pdev);
886
887 pm_runtime_get_sync(qspi->dev);
888 spi_unregister_controller(qspi->ctrl);
889 /* disable qspi */
890 writel_relaxed(0, qspi->io_base + QSPI_CR);
891 stm32_qspi_dma_free(qspi);
892 mutex_destroy(&qspi->lock);
893 pm_runtime_put_noidle(qspi->dev);
894 pm_runtime_disable(qspi->dev);
895 pm_runtime_set_suspended(qspi->dev);
896 pm_runtime_dont_use_autosuspend(qspi->dev);
897 clk_disable_unprepare(qspi->clk);
898 }
899
stm32_qspi_runtime_suspend(struct device * dev)900 static int __maybe_unused stm32_qspi_runtime_suspend(struct device *dev)
901 {
902 struct stm32_qspi *qspi = dev_get_drvdata(dev);
903
904 clk_disable_unprepare(qspi->clk);
905
906 return 0;
907 }
908
stm32_qspi_runtime_resume(struct device * dev)909 static int __maybe_unused stm32_qspi_runtime_resume(struct device *dev)
910 {
911 struct stm32_qspi *qspi = dev_get_drvdata(dev);
912
913 return clk_prepare_enable(qspi->clk);
914 }
915
stm32_qspi_suspend(struct device * dev)916 static int __maybe_unused stm32_qspi_suspend(struct device *dev)
917 {
918 pinctrl_pm_select_sleep_state(dev);
919
920 return pm_runtime_force_suspend(dev);
921 }
922
stm32_qspi_resume(struct device * dev)923 static int __maybe_unused stm32_qspi_resume(struct device *dev)
924 {
925 struct stm32_qspi *qspi = dev_get_drvdata(dev);
926 int ret;
927
928 ret = pm_runtime_force_resume(dev);
929 if (ret < 0)
930 return ret;
931
932 pinctrl_pm_select_default_state(dev);
933
934 ret = pm_runtime_resume_and_get(dev);
935 if (ret < 0)
936 return ret;
937
938 writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR);
939 writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR);
940
941 pm_runtime_mark_last_busy(dev);
942 pm_runtime_put_autosuspend(dev);
943
944 return 0;
945 }
946
947 static const struct dev_pm_ops stm32_qspi_pm_ops = {
948 SET_RUNTIME_PM_OPS(stm32_qspi_runtime_suspend,
949 stm32_qspi_runtime_resume, NULL)
950 SET_SYSTEM_SLEEP_PM_OPS(stm32_qspi_suspend, stm32_qspi_resume)
951 };
952
953 static const struct of_device_id stm32_qspi_match[] = {
954 {.compatible = "st,stm32f469-qspi"},
955 {}
956 };
957 MODULE_DEVICE_TABLE(of, stm32_qspi_match);
958
959 static struct platform_driver stm32_qspi_driver = {
960 .probe = stm32_qspi_probe,
961 .remove = stm32_qspi_remove,
962 .driver = {
963 .name = "stm32-qspi",
964 .of_match_table = stm32_qspi_match,
965 .pm = &stm32_qspi_pm_ops,
966 },
967 };
968 module_platform_driver(stm32_qspi_driver);
969
970 MODULE_AUTHOR("Ludovic Barre <ludovic.barre@st.com>");
971 MODULE_DESCRIPTION("STMicroelectronics STM32 quad spi driver");
972 MODULE_LICENSE("GPL v2");
973