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/linux-6.15/drivers/pci/controller/
Dpcie-mediatek.c1 // SPDX-License-Identifier: GPL-2.0
38 /* PCIe per port registers */
74 /* PCIe V2 per-port registers */
127 (GENMASK(((size) - 1), 0) << ((where) & 0x3))
145 * struct mtk_pcie_soc - differentiate between host generations
160 int (*startup)(struct mtk_pcie_port *port);
161 int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node);
165 * struct mtk_pcie_port - PCIe port information
166 * @base: IO mapped register base
167 * @list: port list
[all …]
Dpcie-apple.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host bridge driver for Apple system-on-chips.
6 * the driver mostly deals MSI mapping and handling of per-port
30 #include <linux/pci-ecam.h>
42 #define CORE_LANE_CFG(port) (0x84000 + 0x4000 * (port)) argument
48 #define CORE_LANE_CTL(port) (0x84004 + 0x4000 * (port)) argument
126 * address (in the bottom 4GB, as the base register is only 32bit).
135 void __iomem *base; member
147 void __iomem *base; member
188 msg->address_hi = upper_32_bits(DOORBELL_ADDR); in apple_msi_compose_msg()
[all …]
Dpcie-mt7621.c1 // SPDX-License-Identifier: GPL-2.0+
35 /* MediaTek-specific configuration registers */
40 /* Host-PCI bridge registers */
67 * struct mt7621_pcie_port - PCIe port information
68 * @base: I/O mapped register base
69 * @list: port list
71 * @clk: pointer to the port clock gate
73 * @pcie_rst: pointer to port reset control
75 * @slot: port slot
76 * @enabled: indicates if port is enabled
[all …]
Dpci-mvebu.c1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
27 #include "../pci-bridge-emul.h"
40 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
94 phys_addr_t base; member
102 void __iomem *base; member
103 u32 port; member
128 static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg) in mvebu_writel() argument
130 writel(val, port->base + reg); in mvebu_writel()
133 static inline u32 mvebu_readl(struct mvebu_pcie_port *port, u32 reg) in mvebu_readl() argument
[all …]
/linux-6.15/drivers/gpio/
Dgpio-mxs.c1 // SPDX-License-Identifier: GPL-2.0+
7 // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
25 #define PINCTRL_DOUT(p) ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
26 #define PINCTRL_DIN(p) ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
27 #define PINCTRL_DOE(p) ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
28 #define PINCTRL_PIN2IRQ(p) ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
29 #define PINCTRL_IRQEN(p) ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
30 #define PINCTRL_IRQLEV(p) ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
31 #define PINCTRL_IRQPOL(p) ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
32 #define PINCTRL_IRQSTAT(p) ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
[all …]
Dgpio-mxc.c1 // SPDX-License-Identifier: GPL-2.0+
8 // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
61 void __iomem *base; member
86 .edge_sel_reg = -EINVAL,
101 .edge_sel_reg = -EINVAL,
123 #define GPIO_DR (port->hwdata->dr_reg)
124 #define GPIO_GDIR (port->hwdata->gdir_reg)
125 #define GPIO_PSR (port->hwdata->psr_reg)
126 #define GPIO_ICR1 (port->hwdata->icr1_reg)
127 #define GPIO_ICR2 (port->hwdata->icr2_reg)
[all …]
Dgpio-vf610.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale vf610 GPIO support through PORT and GPIO
25 /* SoCs has a Port Data Direction Register (PDDR) */
32 void __iomem *base; member
80 { .compatible = "fsl,vf610-gpio", .data = &vf610_data },
81 { .compatible = "fsl,imx7ulp-gpio", .data = &imx_data, },
82 { .compatible = "fsl,imx8ulp-gpio", .data = &imx8ulp_data, },
98 struct vf610_gpio_port *port = in vf610_gpio_irq_handler() local
106 irq_isfr = vf610_gpio_readl(port->base + PORT_ISFR); in vf610_gpio_irq_handler()
109 vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR); in vf610_gpio_irq_handler()
[all …]
Dgpio-gpio-mm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * GPIO driver for the Diamond Systems GPIO-MM
6 * This driver supports the following Diamond Systems devices: GPIO-MM and
7 * GPIO-MM-12.
19 #include "gpio-i8255.h"
26 static unsigned int base[MAX_NUM_GPIOMM]; variable
28 module_param_hw_array(base, uint, ioport, &num_gpiomm, 0);
29 MODULE_PARM_DESC(base, "Diamond Systems GPIO-MM base addresses");
52 "Port 1A0", "Port 1A1", "Port 1A2", "Port 1A3", "Port 1A4", "Port 1A5",
53 "Port 1A6", "Port 1A7", "Port 1B0", "Port 1B1", "Port 1B2", "Port 1B3",
[all …]
Dgpio-tegra186.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2022 NVIDIA Corporation
19 #include <dt-bindings/gpio/tegra186-gpio.h>
20 #include <dt-bindings/gpio/tegra194-gpio.h>
21 #include <dt-bindings/gpio/tegra234-gpio.h>
22 #include <dt-bindings/gpio/tegra241-gpio.h>
74 unsigned int port; member
108 void __iomem *base; member
116 for (i = 0; i < gpio->soc->num_ports; i++) { in tegra186_gpio_get_port()
117 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; in tegra186_gpio_get_port() local
[all …]
/linux-6.15/drivers/phy/mediatek/
Dphy-mtk-mipi-csi-0-5.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/phy/phy.h>
19 #include "phy-mtk-io.h"
20 #include "phy-mtk-mipi-csi-0-5-rx-reg.h"
26 void __iomem *base; member
39 static void mtk_phy_csi_cdphy_ana_eq_tune(void __iomem *base) in mtk_phy_csi_cdphy_ana_eq_tune() argument
41 mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA, RG_CSI0A_L0_T0AB_EQ_IS, 1); in mtk_phy_csi_cdphy_ana_eq_tune()
42 mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA, RG_CSI0A_L0_T0AB_EQ_BW, 1); in mtk_phy_csi_cdphy_ana_eq_tune()
43 mtk_phy_update_field(base + MIPI_RX_ANA1C_CSIXA, RG_CSI0A_L1_T1AB_EQ_IS, 1); in mtk_phy_csi_cdphy_ana_eq_tune()
44 mtk_phy_update_field(base + MIPI_RX_ANA1C_CSIXA, RG_CSI0A_L1_T1AB_EQ_BW, 1); in mtk_phy_csi_cdphy_ana_eq_tune()
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/linux-6.15/drivers/media/pci/intel/ipu6/
Dipu6-isys-jsl-phy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013--2024 Intel Corporation
11 #include "ipu6-bus.h"
12 #include "ipu6-isys.h"
13 #include "ipu6-isys-csi2.h"
14 #include "ipu6-platform-isys-csi2-reg.h"
27 * +---------+ +------+ +-----+
28 * | port0 x4<-----| | | |
29 * | | | port | | |
30 * | port1 x2<-----| | | |
[all …]
/linux-6.15/drivers/hwtracing/intel_th/
Dgth.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2015 Intel Corporation.
25 * struct gth_output - GTH view on an output port
28 * @index: output port number
29 * @port_type: one of GTH_* port type values
41 * struct gth_device - GTH device
43 * @base: register window base address
47 * @master: master/output port assignments
52 void __iomem *base; member
61 static void gth_output_set(struct gth_device *gth, int port, in gth_output_set() argument
[all …]
/linux-6.15/drivers/phy/tegra/
Dxusb.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
19 /* legacy entry points for backwards-compatibility */
59 struct tegra_xusb_lane base; member
65 return container_of(lane, struct tegra_xusb_usb3_lane, base); in to_usb3_lane()
69 struct tegra_xusb_lane base; member
78 return container_of(lane, struct tegra_xusb_usb2_lane, base); in to_usb2_lane()
82 struct tegra_xusb_lane base; member
88 return container_of(lane, struct tegra_xusb_ulpi_lane, base); in to_ulpi_lane()
92 struct tegra_xusb_lane base; member
[all …]
Dxusb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
31 if (args->args_count != 0) in tegra_xusb_pad_of_xlate()
32 return ERR_PTR(-EINVAL); in tegra_xusb_pad_of_xlate()
34 for (i = 0; i < pad->soc->num_lanes; i++) { in tegra_xusb_pad_of_xlate()
35 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate()
38 if (pad->lanes[i]->dev.of_node == args->np) { in tegra_xusb_pad_of_xlate()
39 phy = pad->lanes[i]; in tegra_xusb_pad_of_xlate()
45 phy = ERR_PTR(-ENODEV); in tegra_xusb_pad_of_xlate()
53 .compatible = "nvidia,tegra124-xusb-padctl",
[all …]
/linux-6.15/drivers/net/ethernet/ibm/ehea/
Dehea_ethtool.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 * Jan-Bernd Themann <themann@de.ibm.com>
23 struct ehea_port *port = netdev_priv(dev); in ehea_get_link_ksettings() local
28 ret = ehea_sense_port_attr(port); in ehea_get_link_ksettings()
34 switch (port->port_speed) { in ehea_get_link_ksettings()
48 speed = -1; in ehea_get_link_ksettings()
51 cmd->base.duplex = port->full_duplex == 1 ? in ehea_get_link_ksettings()
55 cmd->base.duplex = DUPLEX_UNKNOWN; in ehea_get_link_ksettings()
57 cmd->base.speed = speed; in ehea_get_link_ksettings()
59 if (cmd->base.speed == SPEED_10000) { in ehea_get_link_ksettings()
[all …]
/linux-6.15/drivers/gpu/drm/i915/display/
Dintel_dvo.c3 * Copyright © 2006-2007 Intel Corporation
63 .port = PORT_C,
70 .port = PORT_C,
77 .port = PORT_C,
84 .port = PORT_A,
91 .port = PORT_C,
98 .port = PORT_C,
106 .port = PORT_B,
113 struct intel_encoder base; member
122 return container_of(encoder, struct intel_dvo, base); in enc_to_dvo()
[all …]
Dintel_ddi.c102 level = intel_bios_hdmi_level_shift(encoder->devdata); in intel_ddi_hdmi_level()
104 level = trans->hdmi_default_entry; in intel_ddi_hdmi_level()
120 * Starting with Haswell, DDI port buffers must be programmed with correct
127 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_prepare_dp_ddi_buffers()
130 enum port port = encoder->port; in hsw_prepare_dp_ddi_buffers() local
133 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in hsw_prepare_dp_ddi_buffers()
134 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) in hsw_prepare_dp_ddi_buffers()
139 intel_bios_dp_boost_level(encoder->devdata)) in hsw_prepare_dp_ddi_buffers()
143 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), in hsw_prepare_dp_ddi_buffers()
144 trans->entries[i].hsw.trans1 | iboost_bit); in hsw_prepare_dp_ddi_buffers()
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/linux-6.15/drivers/net/ethernet/cortina/
Dgemini.c1 // SPDX-License-Identifier: GPL-2.0
11 * Michał Mirosław <mirq-linux@rere.qmqm.pl>
22 #include <linux/dma-mapping.h>
47 #define DRV_NAME "gmac-gemini"
50 static int debug = -1;
87 * struct gmac_queue_page - page buffer per-page info
152 void __iomem *base; member
157 spinlock_t irq_lock; /* Locks IRQ-related registers */
228 struct gemini_ethernet_port *port = netdev_priv(netdev); in gmac_update_config0_reg() local
232 spin_lock_irqsave(&port->config_lock, flags); in gmac_update_config0_reg()
[all …]
/linux-6.15/drivers/pinctrl/actions/
Dpinctrl-owl.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Author: David Liu <liuwei@actions-semi.com>
25 #include <linux/pinctrl/pinconf-generic.h>
31 #include "../pinctrl-utils.h"
32 #include "pinctrl-owl.h"
35 * struct owl_pinctrl - pinctrl state of the device
42 * @base: pinctrl register base address
53 void __iomem *base; member
58 static void owl_update_bits(void __iomem *base, u32 mask, u32 val) in owl_update_bits() argument
62 reg_val = readl_relaxed(base); in owl_update_bits()
[all …]
/linux-6.15/drivers/tty/
Dgoldfish.c1 // SPDX-License-Identifier: GPL-2.0
19 #include <linux/dma-mapping.h>
37 struct tty_port port; member
39 void __iomem *base; member
57 void __iomem *base = qtty->base; in do_rw_io() local
59 spin_lock_irqsave(&qtty->lock, irq_flags); in do_rw_io()
60 gf_write_ptr((void *)address, base + GOLDFISH_TTY_REG_DATA_PTR, in do_rw_io()
61 base + GOLDFISH_TTY_REG_DATA_PTR_HIGH); in do_rw_io()
62 gf_iowrite32(count, base + GOLDFISH_TTY_REG_DATA_LEN); in do_rw_io()
66 base + GOLDFISH_TTY_REG_CMD); in do_rw_io()
[all …]
/linux-6.15/drivers/tty/serial/
Drp2.c1 // SPDX-License-Identifier: GPL-2.0
12 * rocketport_infinity_express-linux-1.20.tar.gz
13 * Copyright (C) 2004-2011 Comtrol, Inc.
44 #define ALL_PORTS_MASK (BIT(PORTS_PER_ASIC) - 1)
75 /* port registers */
84 /* This lets uart_insert_char() drop bytes received on a !CREAD port */
179 struct uart_port port; member
183 void __iomem *base; member
205 *ports = id->driver_data >> 8; in rp2_decode_cap()
206 *smpte = id->driver_data & 0xff; in rp2_decode_cap()
[all …]
/linux-6.15/Documentation/devicetree/bindings/net/
Dhisilicon-hns-dsaf.txt4 - compatible: should be "hisilicon,hns-dsaf-v1" or "hisilicon,hns-dsaf-v2".
5 "hisilicon,hns-dsaf-v1" is for hip05.
6 "hisilicon,hns-dsaf-v2" is for Hi1610 and Hi1612.
7 - mode: dsa fabric mode string. only support one of dsaf modes like these:
8 "2port-64vf",
9 "6port-16rss",
10 "6port-16vf",
11 "single-port".
12 - interrupts: should contain the DSA Fabric and rcb interrupt.
13 - reg: specifies base physical address(es) and size of the device registers.
[all …]
/linux-6.15/drivers/hsi/controllers/
Domap_ssi_port.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* OMAP SSI port driver.
12 #include <linux/dma-mapping.h>
33 static inline unsigned int ssi_wakein(struct hsi_port *port) in ssi_wakein() argument
35 struct omap_ssi_port *omap_port = hsi_port_drvdata(port); in ssi_wakein()
36 return gpiod_get_value(omap_port->wake_gpio); in ssi_wakein()
40 static void ssi_debug_remove_port(struct hsi_port *port) in ssi_debug_remove_port() argument
42 struct omap_ssi_port *omap_port = hsi_port_drvdata(port); in ssi_debug_remove_port()
44 debugfs_remove_recursive(omap_port->dir); in ssi_debug_remove_port()
49 struct hsi_port *port = m->private; in ssi_port_regs_show() local
[all …]
/linux-6.15/Documentation/networking/dsa/
Dsja1105.rst8 The NXP SJA1105 is a family of 10 SPI-managed automotive switches:
10 - SJA1105E: First generation, no TTEthernet
11 - SJA1105T: First generation, TTEthernet
12 - SJA1105P: Second generation, no TTEthernet, no SGMII
13 - SJA1105Q: Second generation, TTEthernet, no SGMII
14 - SJA1105R: Second generation, no TTEthernet, SGMII
15 - SJA1105S: Second generation, TTEthernet, SGMII
16 - SJA1110A: Third generation, TTEthernet, SGMII, integrated 100base-T1 and
17 100base-TX PHYs
18 - SJA1110B: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TX
[all …]
/linux-6.15/drivers/hwtracing/coresight/
Dcoresight-tpda.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved.
18 #include "coresight-priv.h"
19 #include "coresight-tpda.h"
20 #include "coresight-trace-id.h"
21 #include "coresight-tpdm.h"
28 (csdev->subtype.source_subtype == in coresight_device_is_tpdm()
34 struct tpda_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); in tpda_clear_element_size()
36 drvdata->dsb_esize = 0; in tpda_clear_element_size()
37 drvdata->cmb_esize = 0; in tpda_clear_element_size()
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