1 // SPDX-License-Identifier: GPL-2.0-only
3  * Copyright (C) 2013--2024 Intel Corporation
11 #include "ipu6-bus.h"
12 #include "ipu6-isys.h"
13 #include "ipu6-isys-csi2.h"
14 #include "ipu6-platform-isys-csi2-reg.h"
27  * +---------+     +------+ +-----+
28  * | port0 x4<-----|      | |     |
29  * |         |     | port | |     |
30  * | port1 x2<-----|      | |     |
31  * |         |     |      <-| PHY |
32  * | port2 x4<-----|      | |     |
34  * | port3 x2<-----|      | |     |
35  * +---------+     +------+ +-----+
48 /* port, nlanes, bbindex, portcfg */
63 					      unsigned int port,  in ipu6_isys_csi2_phy_config_by_port()  argument
66 	struct device *dev = &isys->adev->auxdev.dev;  in ipu6_isys_csi2_phy_config_by_port()
67 	void __iomem *base = isys->adev->isp->base;  in ipu6_isys_csi2_phy_config_by_port()  local
71 	dev_dbg(dev, "port %u with %u lanes", port, nlanes);  in ipu6_isys_csi2_phy_config_by_port()
77 		val = readl(base + reg);  in ipu6_isys_csi2_phy_config_by_port()
79 		writel(val, base + reg);  in ipu6_isys_csi2_phy_config_by_port()
83 		val = readl(base + reg);  in ipu6_isys_csi2_phy_config_by_port()
85 		writel(val, base + reg);  in ipu6_isys_csi2_phy_config_by_port()
89 		val = readl(base + reg);  in ipu6_isys_csi2_phy_config_by_port()
91 		writel(val, base + reg);  in ipu6_isys_csi2_phy_config_by_port()
95 		val = readl(base + reg);  in ipu6_isys_csi2_phy_config_by_port()
97 		writel(val, base + reg);  in ipu6_isys_csi2_phy_config_by_port()
102 		if (phy_port_cfg[i][0] == port &&  in ipu6_isys_csi2_phy_config_by_port()
106 			val = readl(base + reg);  in ipu6_isys_csi2_phy_config_by_port()
108 			writel(val, base + reg);  in ipu6_isys_csi2_phy_config_by_port()
115 	void __iomem *base = isys->adev->isp->base;  in ipu6_isys_csi2_rx_control()  local
119 	val = readl(base + reg);  in ipu6_isys_csi2_rx_control()
121 	writel(val, base + CSI2_HUB_GPREG_SIP0_CSI_RX_A_CONTROL);  in ipu6_isys_csi2_rx_control()
124 	val = readl(base + reg);  in ipu6_isys_csi2_rx_control()
126 	writel(val, base + CSI2_HUB_GPREG_SIP0_CSI_RX_B_CONTROL);  in ipu6_isys_csi2_rx_control()
129 	val = readl(base + reg);  in ipu6_isys_csi2_rx_control()
131 	writel(val, base + CSI2_HUB_GPREG_SIP1_CSI_RX_A_CONTROL);  in ipu6_isys_csi2_rx_control()
134 	val = readl(base + reg);  in ipu6_isys_csi2_rx_control()
136 	writel(val, base + CSI2_HUB_GPREG_SIP1_CSI_RX_B_CONTROL);  in ipu6_isys_csi2_rx_control()
140 				       unsigned int port, unsigned int nlanes)  in ipu6_isys_csi2_set_port_cfg()  argument
142 	struct device *dev = &isys->adev->auxdev.dev;  in ipu6_isys_csi2_set_port_cfg()
143 	unsigned int sip = port / 2;  in ipu6_isys_csi2_set_port_cfg()
158 		return -EINVAL;  in ipu6_isys_csi2_set_port_cfg()
161 	dev_dbg(dev, "port config for port %u with %u lanes\n",	port, nlanes);  in ipu6_isys_csi2_set_port_cfg()
164 	       isys->pdata->base + CSI2_HUB_GPREG_SIP_FB_PORT_CFG(sip));  in ipu6_isys_csi2_set_port_cfg()
172 			  unsigned int port, unsigned int nlanes)  in ipu6_isys_csi2_set_timing()  argument
174 	struct device *dev = &isys->adev->auxdev.dev;  in ipu6_isys_csi2_set_timing()
179 	port_base = (port % 2) ? CSI2_SIP_TOP_CSI_RX_PORT_BASE_1(port) :  in ipu6_isys_csi2_set_timing()
180 		CSI2_SIP_TOP_CSI_RX_PORT_BASE_0(port);  in ipu6_isys_csi2_set_timing()
182 	dev_dbg(dev, "set timing for port %u with %u lanes\n", port, nlanes);  in ipu6_isys_csi2_set_timing()
184 	reg = isys->pdata->base + port_base;  in ipu6_isys_csi2_set_timing()
187 	writel(timing->ctermen, reg);  in ipu6_isys_csi2_set_timing()
189 	reg = isys->pdata->base + port_base;  in ipu6_isys_csi2_set_timing()
191 	writel(timing->csettle, reg);  in ipu6_isys_csi2_set_timing()
194 		reg = isys->pdata->base + port_base;  in ipu6_isys_csi2_set_timing()
196 		writel(timing->dtermen, reg);  in ipu6_isys_csi2_set_timing()
198 		reg = isys->pdata->base + port_base;  in ipu6_isys_csi2_set_timing()
200 		writel(timing->dsettle, reg);  in ipu6_isys_csi2_set_timing()
210 	struct device *dev = &isys->adev->auxdev.dev;  in ipu6_isys_jsl_phy_set_power()
211 	void __iomem *isys_base = isys->pdata->base;  in ipu6_isys_jsl_phy_set_power()
214 	u32 port;  in ipu6_isys_jsl_phy_set_power()  local
219 	port = cfg->port;  in ipu6_isys_jsl_phy_set_power()
220 	nlanes = cfg->nlanes;  in ipu6_isys_jsl_phy_set_power()
222 	if (!isys_base || port >= isys->pdata->ipdata->csi2.nports) {  in ipu6_isys_jsl_phy_set_power()
223 		dev_warn(dev, "invalid port ID %d\n", port);  in ipu6_isys_jsl_phy_set_power()
224 		return -EINVAL;  in ipu6_isys_jsl_phy_set_power()
227 	ipu6_isys_csi2_phy_config_by_port(isys, port, nlanes);  in ipu6_isys_jsl_phy_set_power()
230 	       isys->pdata->base + CSI2_HUB_GPREG_DPHY_TIMER_INCR);  in ipu6_isys_jsl_phy_set_power()
232 	/* set port cfg and rx timing */  in ipu6_isys_jsl_phy_set_power()
233 	ipu6_isys_csi2_set_timing(isys, timing, port, nlanes);  in ipu6_isys_jsl_phy_set_power()
235 	ret = ipu6_isys_csi2_set_port_cfg(isys, port, nlanes);  in ipu6_isys_jsl_phy_set_power()