| /qemu/tests/qtest/ |
| H A D | stm32l4x5_gpio-test.c | 86 static inline void *test_data(uint32_t gpio_addr, uint8_t pin) in test_data() argument
88 return (void *)(uintptr_t)((gpio_addr & GPIO_ADDR_MASK) | (pin & PIN_MASK)); in test_data()
105 unsigned int pin, uint32_t value) in gpio_set_bit() argument
107 uint32_t mask = 0xFFFFFFFF & ~(0x1 << pin); in gpio_set_bit()
108 gpio_writel(gpio, reg, (gpio_readl(gpio, reg) & mask) | value << pin); in gpio_set_bit()
112 unsigned int pin, uint32_t value) in gpio_set_2bits() argument
114 uint32_t offset = 2 * pin; in gpio_set_2bits()
186 * (in case the pin is in output mode). in test_idr_reset_value()
279 unsigned int pin = test_pin(data); in test_gpio_output_mode() local
286 gpio_set_bit(gpio, ODR, pin, 1); in test_gpio_output_mode()
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| H A D | dm163-test.c | 35 /* Configure output mode for pin PB1 */ in rise_gpio_pin_dck()
43 /* Configure output mode for pin PB1 */ in lower_gpio_pin_dck()
51 /* Configure output mode for pin PC5 */ in rise_gpio_pin_selbk()
59 /* Configure output mode for pin PC5 */ in lower_gpio_pin_selbk()
67 /* Configure output mode for pin PC4 */ in rise_gpio_pin_lat_b()
75 /* Configure output mode for pin PC4 */ in lower_gpio_pin_lat_b()
83 /* Configure output mode for pin PC3 */ in rise_gpio_pin_rst_b()
91 /* Configure output mode for pin PC3 */ in lower_gpio_pin_rst_b()
99 /* Configure output mode for pin PA4 */ in rise_gpio_pin_sin()
107 /* Configure output mode for pin PA4 */ in lower_gpio_pin_sin()
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| H A D | ast2700-gpio-test.c | 22 uint32_t pin = 0; in test_output_pins() local
26 offset = base + (pin * 4); in test_output_pins()
37 pin++; in test_output_pins()
50 uint32_t pin = 0; in test_input_pins() local
55 offset = base + (pin * 4); in test_input_pins()
68 pin++; in test_input_pins()
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| H A D | pnv-host-i2c-test.c | 166 static void pnv_i2c_pca9554_set_pin(PnvI2cDev *dev, int pin, bool high) in pnv_i2c_pca9554_set_pin() argument
170 uint8_t mask = 0x1 << pin; in pnv_i2c_pca9554_set_pin()
171 uint8_t new_value = ((high) ? 1 : 0) << pin; in pnv_i2c_pca9554_set_pin()
218 /* Check that setting pin values and polarity changes inputs as expected */
271 static void pnv_i2c_pca9552_set_pin(PnvI2cDev *dev, int pin, bool high) in pnv_i2c_pca9552_set_pin() argument
275 uint8_t reg = PCA9552_LS0 + (pin / 4); in pnv_i2c_pca9552_set_pin()
276 uint8_t shift = (pin % 4) * 2; in pnv_i2c_pca9552_set_pin()
320 /* set pin 0 low */ in pnv_i2c_pca552_set_pins()
327 /* set pin 1 low */ in pnv_i2c_pca552_set_pins()
334 /* set pin 2 low */ in pnv_i2c_pca552_set_pins()
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| /qemu/hw/gpio/ |
| H A D | pca9554.c | 70 /* update irq state only if pin state changed */ in pca9554_update_pin_input()
152 int pin, rc; in pca9554_get_pin() local
155 rc = sscanf(name, "pin%2d", &pin); in pca9554_get_pin()
160 if (pin < 0 || pin >= PCA9554_PIN_COUNT) { in pca9554_get_pin()
161 error_setg(errp, "%s invalid pin %s", __func__, name); in pca9554_get_pin()
167 state = (state >> pin) & 0x1; in pca9554_get_pin()
175 int pin, rc, val; in pca9554_set_pin() local
182 rc = sscanf(name, "pin%2d", &pin); in pca9554_set_pin()
187 if (pin < 0 || pin >= PCA9554_PIN_COUNT) { in pca9554_set_pin()
188 error_setg(errp, "%s invalid pin %s", __func__, name); in pca9554_set_pin()
[all …]
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| H A D | stm32l4x5_gpio.c | 49 static bool is_pull_up(Stm32l4x5GpioState *s, unsigned pin) in is_pull_up() argument
51 return extract32(s->pupdr, 2 * pin, 2) == 1; in is_pull_up()
54 static bool is_pull_down(Stm32l4x5GpioState *s, unsigned pin) in is_pull_down() argument
56 return extract32(s->pupdr, 2 * pin, 2) == 2; in is_pull_down()
59 static bool is_output(Stm32l4x5GpioState *s, unsigned pin) in is_output() argument
61 return extract32(s->moder, 2 * pin, 2) == 1; in is_output()
64 static bool is_open_drain(Stm32l4x5GpioState *s, unsigned pin) in is_open_drain() argument
66 return extract32(s->otyper, pin, 1) == 1; in is_open_drain()
69 static bool is_push_pull(Stm32l4x5GpioState *s, unsigned pin) in is_push_pull() argument
71 return extract32(s->otyper, pin, 1) == 0; in is_push_pull()
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| H A D | pca9552.c | 52 static uint8_t pca955x_pin_get_config(PCA955xState *s, int pin) in pca955x_pin_get_config() argument
54 uint8_t reg = PCA9552_LS0 + (pin / 4); in pca955x_pin_get_config()
55 uint8_t shift = (pin % 4) << 1; in pca955x_pin_get_config()
122 /* Pin is set to 0V to turn on LED */ in pca955x_update_pin_input()
127 * Pin is set to Hi-Z to turn off LED and in pca955x_update_pin_input()
144 /* update irq state only if pin state changed */ in pca955x_update_pin_input()
398 static void pca955x_set_ext_state(PCA955xState *s, int pin, int level) in pca955x_set_ext_state() argument
400 if (s->ext_state[pin] != level) { in pca955x_set_ext_state()
402 s->ext_state[pin] = level; in pca955x_set_ext_state()
408 static void pca955x_gpio_in_handler(void *opaque, int pin, int level) in pca955x_gpio_in_handler() argument
[all …]
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| H A D | aspeed_gpio.c | 353 uint32_t pin) in aspeed_gpio_get_pin_level() argument
356 uint32_t pin_mask = 1 << pin; in aspeed_gpio_get_pin_level()
364 uint32_t pin, bool level) in aspeed_gpio_set_pin_level() argument
367 uint32_t pin_mask = 1 << pin; in aspeed_gpio_set_pin_level()
702 * where data is the value attempted to be written to the pin: in aspeed_gpio_write_index_mode()
703 * pin type | input mask | output mask | expected value in aspeed_gpio_write_index_mode()
708 * no pin | 0 | 0 | 0 in aspeed_gpio_write_index_mode()
857 * where data is the value attempted to be written to the pin: in aspeed_gpio_write()
858 * pin type | input mask | output mask | expected value in aspeed_gpio_write()
863 * no pin | 0 | 0 | 0 in aspeed_gpio_write()
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| H A D | sifive_gpio.c | 25 uint32_t pin; in update_output_irq() local
33 pin = 1 << i; in update_output_irq()
34 qemu_set_irq(s->irq[i], (pending & pin) != 0); in update_output_irq()
35 trace_sifive_gpio_update_output_irq(i, (pending & pin) != 0); in update_output_irq()
63 /* Pin both driven externally and internally */ in update_state()
65 qemu_log_mask(LOG_GUEST_ERROR, "GPIO pin %zu short circuited\n", i); in update_state()
69 /* The pin is driven by external device */ in update_state()
72 /* The pin is driven by internal circuit */ in update_state()
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| H A D | npcm7xx_gpio.c | 97 /* Calculate level of each pin driven by GPIO controller. */ in npcm7xx_gpio_update_pins()
103 * If a pin is driven to opposite levels by the GPIO controller and the in npcm7xx_gpio_update_pins()
305 qemu_log_mask(LOG_UNIMP, "%s: Per-pin lock is not implemented\n", in npcm7xx_gpio_regs_write()
389 /* Bit n set => pin n has pullup enabled by default. */
391 /* Bit n set => pin n has pulldown enabled by default. */
393 /* Bit n set => pin n has high slew rate by default. */
395 /* Bit n set => pin n has high drive strength by default. */
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| /qemu/hw/intc/ |
| H A D | mips_gic.c | 25 static void mips_gic_set_vp_irq(MIPSGICState *gic, int vp, int pin) in mips_gic_set_vp_irq() argument
30 /* ORing pending registers sharing same pin */ in mips_gic_set_vp_irq()
32 if ((gic->irq_state[i].map_pin & GIC_MAP_MSK) == pin && in mips_gic_set_vp_irq()
42 if (((gic->vps[vp].compare_map & GIC_MAP_MSK) == pin) && in mips_gic_set_vp_irq()
50 pin + GIC_CPU_PIN_OFFSET, in mips_gic_set_vp_irq()
53 qemu_set_irq(gic->vps[vp].env->irq[pin + GIC_CPU_PIN_OFFSET], in mips_gic_set_vp_irq()
61 int pin = gic->irq_state[n_IRQ].map_pin & GIC_MAP_MSK; in gic_update_pin_for_irq() local
66 mips_gic_set_vp_irq(gic, vp, pin); in gic_update_pin_for_irq()
138 /* each bit represents pending status for an interrupt pin */ in gic_read()
146 /* each bit represents status for an interrupt pin */ in gic_read()
[all …]
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| H A D | loongarch_extioi_common.c | 37 int pin, index; in loongarch_extioi_cpu_plug() local
57 for (pin = 0; pin < LS3A_INTC_IP; pin++) { in loongarch_extioi_cpu_plug()
58 qdev_connect_gpio_out(DEVICE(s), index * LS3A_INTC_IP + pin, in loongarch_extioi_cpu_plug()
59 qdev_get_gpio_in(dev, pin + 2)); in loongarch_extioi_cpu_plug()
90 int i, pin; in loongarch_extioi_common_realize() local
105 for (pin = 0; pin < LS3A_INTC_IP; pin++) { in loongarch_extioi_common_realize()
106 qdev_init_gpio_out(dev, &s->cpu[i].parent_irq[pin], 1); in loongarch_extioi_common_realize()
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| /qemu/hw/ppc/ |
| H A D | ppc.c | 73 static void ppc6xx_set_irq(void *opaque, int pin, int level) in ppc6xx_set_irq() argument
79 trace_ppc_irq_set(env, pin, level); in ppc6xx_set_irq()
81 cur_level = (env->irq_input_state >> pin) & 1; in ppc6xx_set_irq()
86 switch (pin) { in ppc6xx_set_irq()
118 /* XXX: TODO: relay the signal to CKSTP_OUT pin */ in ppc6xx_set_irq()
140 env->irq_input_state |= 1 << pin; in ppc6xx_set_irq()
142 env->irq_input_state &= ~(1 << pin); in ppc6xx_set_irq()
153 static void ppc970_set_irq(void *opaque, int pin, int level) in ppc970_set_irq() argument
159 trace_ppc_irq_set(env, pin, level); in ppc970_set_irq()
161 cur_level = (env->irq_input_state >> pin) & 1; in ppc970_set_irq()
[all …]
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| /qemu/rust/qemu-api/src/ |
| H A D | timer.rs | 7 pin::Pin,
49 self: Pin<&'timer mut Self>, in init_full()
91 // take a Pin<&mut Self>, therefore the timer is pinned in modify()
97 // take a Pin<&mut Self>, therefore the timer is pinned in delete()
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| /qemu/hw/arm/ |
| H A D | b-l475e-iot01a.c | 40 * Here the DM163 input pin EN isn't connected to the STM32L4x5
42 * this pin to drive the RGB matrix.
78 unsigned gpio, pin; in bl475e_init() local
106 pin = dm163_input[i] % GPIO_NUM_PINS; in bl475e_init()
107 qdev_connect_gpio_out(DEVICE(&s->soc.gpio[gpio]), pin, in bl475e_init()
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| /qemu/hw/pci-host/ |
| H A D | ppce500.c | 341 static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int pin) in mpc85xx_pci_map_irq() argument
346 ret = ppce500_pci_map_irq_slot(devno, pin); in mpc85xx_pci_map_irq()
349 pci_dev->devfn, pin, ret, devno); in mpc85xx_pci_map_irq()
354 static void mpc85xx_pci_set_irq(void *opaque, int pin, int level) in mpc85xx_pci_set_irq() argument
359 pci_debug("%s: PCI irq %d, level:%d\n", __func__, pin , level); in mpc85xx_pci_set_irq()
361 qemu_set_irq(pic[pin], level); in mpc85xx_pci_set_irq()
364 static PCIINTxRoute e500_route_intx_pin_to_irq(void *opaque, int pin) in e500_route_intx_pin_to_irq() argument
370 route.irq = s->irq_num[pin]; in e500_route_intx_pin_to_irq()
372 pci_debug("%s: PCI irq-pin = %d, irq_num= %d\n", __func__, pin, route.irq); in e500_route_intx_pin_to_irq()
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| /qemu/hw/vfio/ |
| H A D | platform.c | 69 intp->pin = info.index; in vfio_init_intp()
122 if (!vfio_device_irq_set_signaling(vbasedev, intp->pin, 0, in vfio_set_trigger_eventfd()
174 trace_vfio_platform_intp_mmap_enable(tmp->pin); in vfio_intp_mmap_enable()
196 trace_vfio_platform_intp_inject_pending_lockheld(intp->pin, in vfio_intp_inject_pending_lockheld()
236 trace_vfio_intp_interrupt_set_pending(intp->pin); in vfio_intp_interrupt()
243 trace_vfio_platform_intp_interrupt(intp->pin, in vfio_intp_interrupt()
295 trace_vfio_platform_eoi(intp->pin, in vfio_platform_eoi()
304 vfio_device_irq_unmask(vbasedev, intp->pin); in vfio_platform_eoi()
360 if (!vfio_device_irq_set_signaling(vbasedev, intp->pin, 0, in vfio_set_resample_eventfd()
406 trace_vfio_platform_start_level_irqfd_injection(intp->pin, in vfio_start_irqfd_injection()
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| H A D | trace-events | 4 vfio_intx_interrupt(const char *name, char line) " (%s) Pin %c"
129 vfio_platform_eoi(int pin, int fd) "EOI IRQ pin %d (fd=%d)"
130 vfio_platform_intp_mmap_enable(int pin) "IRQ #%d still active, stay in slow path"
131 vfio_platform_intp_interrupt(int pin, int fd) "Inject IRQ #%d (fd = %d)"
132 vfio_platform_intp_inject_pending_lockheld(int pin, int fd) "Inject pending IRQ #%d (fd = %d)"
133 vfio_platform_populate_interrupts(int pin, int count, int flags) "- IRQ index %d: count %d, flags=0…
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| /qemu/docs/specs/ |
| H A D | pci-serial.rst | 23 Wired to pin A.
37 Wired to pin A.
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| H A D | aspeed-intc.rst | 22 from INTCIO and connected to INTC at input pin 0 and output pins 0 to 9 for
27 The orgate has interrupt sources ranging from 0 to 31, with its output pin
28 connected to INTCIO "T0 GICINT_196". The output pin is then connected to INTC
29 "GIC_192_201" at bit 4, and its bit 4 output pin is connected to GIC 196.
31 INTC GIC_192_201 Output Pin Mapping
58 The orgate has interrupt sources ranging from 0 to 31, with its output pin
59 connected to INTC. The output pin is then connected to GIC 132.
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| /qemu/include/hw/gpio/ |
| H A D | sifive_gpio.h | 55 uint32_t value; /* Actual value of the pin */
58 uint32_t port; /* Pin value requested by the user */
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| H A D | nrf51_gpio.h | 6 * + Unnamed GPIO inputs 0-31: Set tri-state input level for GPIO pin.
18 * + Pin SENSEing is not modeled/implemented.
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| H A D | stm32l4x5_gpio.h | 57 * The pin must not be in push-pull output mode,
68 qemu_irq pin[GPIO_NUM_PINS]; member
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| /qemu/include/hw/char/ |
| H A D | imx_serial.h | 38 #define USR1_RTSS (1<<14) /* RTS pin status */
40 #define USR1_RTSD (1<<12) /* RTS delta: pin changed state */
48 #define USR1_AWAKE (1<<4) /* Falling edge detected on RXd pin */
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| /qemu/python/tests/ |
| H A D | minreqs.txt | 11 # When adding new dependencies, pin the very oldest non-yanked version
15 # also pin setuptools to version 70 or below. Otherwise, the
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