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e38d3c5c |
| 31-Aug-2020 |
Eduardo Habkost <ehabkost@redhat.com> |
sifive: Use DECLARE_*CHECKER* macros
$ ./scripts/codeconverter/converter.py -i \ --pattern=TypeCheckMacro $(git grep -l '' -- '*.[ch]')
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Revi
sifive: Use DECLARE_*CHECKER* macros
$ ./scripts/codeconverter/converter.py -i \ --pattern=TypeCheckMacro $(git grep -l '' -- '*.[ch]')
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20200831210740.126168-12-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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ac900ede |
| 31-Aug-2020 |
Eduardo Habkost <ehabkost@redhat.com> |
sifive: Move QOM typedefs and add missing includes
Some typedefs and macros are defined after the type check macros. This makes it difficult to automatically replace their definitions with OBJECT_DE
sifive: Move QOM typedefs and add missing includes
Some typedefs and macros are defined after the type check macros. This makes it difficult to automatically replace their definitions with OBJECT_DECLARE_TYPE.
Patch generated using:
$ ./scripts/codeconverter/converter.py -i \ --pattern=QOMStructTypedefSplit $(git grep -l '' -- '*.[ch]')
which will split "typdef struct { ... } TypedefName" declarations.
Followed by:
$ ./scripts/codeconverter/converter.py -i --pattern=MoveSymbols \ $(git grep -l '' -- '*.[ch]')
which will: - move the typedefs and #defines above the type check macros - add missing #include "qom/object.h" lines if necessary
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20200831210740.126168-9-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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4921a0ce |
| 03-Sep-2020 |
Bin Meng <bin.meng@windriver.com> |
hw/riscv: Move sifive_gpio model to hw/gpio
This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_
hw/riscv: Move sifive_gpio model to hw/gpio
This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_gpio model to hw/gpio directory.
Note this also removes the trace-events in the hw/riscv directory, since gpio is the only supported trace target in that directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1599129623-68957-5-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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4bb216f6 |
| 08-Jun-2020 |
Bin Meng <bin.meng@windriver.com> |
hw/riscv: sifive_gpio: Add a new 'ngpio' property
Add a new property to represent the number of GPIO pins supported by the GPIO controller.
Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed
hw/riscv: sifive_gpio: Add a new 'ngpio' property
Add a new property to represent the number of GPIO pins supported by the GPIO controller.
Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1591625864-31494-7-git-send-email-bmeng.cn@gmail.com Message-Id: <1591625864-31494-7-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2e30ccb4 |
| 08-Jun-2020 |
Bin Meng <bin.meng@windriver.com> |
hw/riscv: sifive_gpio: Clean up the codes
Do various minor clean-ups to the exisiting codes for:
- coding convention conformance - remove unnecessary blank lines - spell SiFive correctly
Signed-of
hw/riscv: sifive_gpio: Clean up the codes
Do various minor clean-ups to the exisiting codes for:
- coding convention conformance - remove unnecessary blank lines - spell SiFive correctly
Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1591625864-31494-6-git-send-email-bmeng.cn@gmail.com Message-Id: <1591625864-31494-6-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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30efbf33 |
| 12-Feb-2019 |
Fabien Chouteau <chouteau@adacore.com> |
SiFive RISC-V GPIO Device
QEMU model of the GPIO device on the SiFive E300 series SOCs.
The pins are not used by a board definition yet, however this implementation can already be used to trigger G
SiFive RISC-V GPIO Device
QEMU model of the GPIO device on the SiFive E300 series SOCs.
The pins are not used by a board definition yet, however this implementation can already be used to trigger GPIO interrupts from the software by configuring a pin as both output and input.
Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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