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/linux-5.10/Documentation/devicetree/bindings/display/msm/
Ddsi.txt1 Qualcomm Technologies Inc. adreno/snapdragon DSI output
3 DSI Controller:
5 - compatible:
6 * "qcom,mdss-dsi-ctrl"
7 - reg: Physical base address and length of the registers of controller
8 - reg-names: The names of register regions. The following regions are required:
10 - interrupts: The interrupt signal from the DSI block.
11 - power-domains: Should be <&mmcc MDSS_GDSC>.
12 - clocks: Phandles to device clocks.
13 - clock-names: the following clocks are required:
[all …]
/linux-5.10/Documentation/devicetree/bindings/display/exynos/
Dexynos_dsim.txt1 Exynos MIPI DSI Master
4 - compatible: value should be one of the following
5 "samsung,exynos3250-mipi-dsi" /* for Exynos3250/3472 SoCs */
6 "samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */
7 "samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */
8 "samsung,exynos5422-mipi-dsi" /* for Exynos5422/5800 SoCs */
9 "samsung,exynos5433-mipi-dsi" /* for Exynos5433 SoCs */
10 - reg: physical base address and length of the registers set for the device
11 - interrupts: should contain DSI interrupt
12 - clocks: list of clock specifiers, must contain an entry for each required
[all …]
/linux-5.10/Documentation/devicetree/bindings/display/
Dallwinner,sun6i-a31-mipi-dsi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun6i-a31-mipi-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A31 MIPI-DSI Controller Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 - allwinner,sun6i-a31-mipi-dsi
17 - allwinner,sun50i-a64-mipi-dsi
29 - description: Bus Clock
[all …]
Dst,stm32-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/st,stm32-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 DSI host controller
10 - Philippe Cornu <philippe.cornu@st.com>
11 - Yannick Fertre <yannick.fertre@st.com>
14 The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI-DSI host controller.
17 - $ref: dsi-controller.yaml#
21 const: st,stm32-dsi
[all …]
/linux-5.10/Documentation/devicetree/bindings/display/ti/
Dti,omap4-dss.txt4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
8 --------
11 - compatible: "ti,omap4-dss"
12 - reg: address and length of the register space
13 - ti,hwmods: "dss_core"
14 - clocks: handle to fclk
15 - clock-names: "fck"
18 - DISPC
21 - DSS Submodules: RFBI, VENC, DSI, HDMI
22 - Video port for DPI output
[all …]
Dti,omap5-dss.txt4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
8 --------
11 - compatible: "ti,omap5-dss"
12 - reg: address and length of the register space
13 - ti,hwmods: "dss_core"
14 - clocks: handle to fclk
15 - clock-names: "fck"
18 - DISPC
21 - DSS Submodules: RFBI, DSI, HDMI
22 - Video port for DPI output
[all …]
Dti,omap3-dss.txt4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
8 --------
11 - compatible: "ti,omap3-dss"
12 - reg: address and length of the register space
13 - ti,hwmods: "dss_core"
14 - clocks: handle to fclk
15 - clock-names: "fck"
18 - Video ports:
19 - Port 0: DPI output
20 - Port 1: SDI output
[all …]
/linux-5.10/Documentation/devicetree/bindings/clock/
Dqcom,mmcc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeffrey Hugo <jhugo@codeaurora.org>
11 - Taniya Das <tdas@codeaurora.org>
20 - qcom,mmcc-apq8064
21 - qcom,mmcc-apq8084
22 - qcom,mmcc-msm8660
23 - qcom,mmcc-msm8960
24 - qcom,mmcc-msm8974
[all …]
/linux-5.10/Documentation/devicetree/bindings/display/bridge/
Dnwl-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Northwest Logic MIPI-DSI controller on i.MX SoCs
10 - Guido Gúnther <agx@sigxcpu.org>
11 - Robert Chiras <robert.chiras@nxp.com>
14 NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for
15 the SOCs NWL MIPI-DSI host controller.
18 - $ref: ../dsi-controller.yaml#
[all …]
Dlontium,lt9611.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinod Koul <vkoul@kernel.org>
13 The LT9611 is a bridge device which converts DSI to HDMI
18 - lontium,lt9611
23 "#sound-dai-cells":
29 reset-gpios:
33 vdd-supply:
34 description: Regulator for 1.8V MIPI phy power.
[all …]
/linux-5.10/drivers/gpu/drm/bridge/
Dtc358775.c1 // SPDX-License-Identifier: GPL-2.0
3 * TC358775 DSI to LVDS bridge driver
35 /* DSI D-PHY Layer Registers */
50 /* DSI PPI Layer Registers */
51 #define PPI_STARTPPI 0x0104 /* START control bit of PPI-TX function. */
58 #define PPI_TX_RX_TA 0x013C /* DSI Bus Turn Around timing parameters */
72 #define CLS_PRE 0x0180 /* Digital Counter inside of PHY IO */
73 #define D0S_PRE 0x0184 /* Digital Counter inside of PHY IO */
74 #define D1S_PRE 0x0188 /* Digital Counter inside of PHY IO */
75 #define D2S_PRE 0x018C /* Digital Counter inside of PHY IO */
[all …]
Dparade-ps8640.c1 // SPDX-License-Identifier: GPL-2.0-only
37 * page[3]: for DSI Link Control1
38 * page[4]: for MIPI Phy
40 * page[6]: for DSI Link Control2
63 struct mipi_dsi_device *dsi; member
79 struct i2c_client *client = ps_bridge->page[PAGE3_DSI_CNTL1]; in ps8640_bridge_vdo_control()
97 struct i2c_client *client = ps_bridge->page[PAGE2_TOP_CNTL]; in ps8640_bridge_poweron()
101 if (ps_bridge->powered) in ps8640_bridge_poweron()
104 ret = regulator_bulk_enable(ARRAY_SIZE(ps_bridge->supplies), in ps8640_bridge_poweron()
105 ps_bridge->supplies); in ps8640_bridge_poweron()
[all …]
Dtc358764.c1 // SPDX-License-Identifier: GPL-2.0
28 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
42 /* DSI layer registers */
43 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
115 #define LV_PHY0 0x04A0 /* LVDS PHY 0 */
116 #define LV_PHY0_RST(v) FLD_VAL(v, 22, 22) /* PHY reset */
125 #define SYS_RST_I2CS BIT(0) /* Reset I2C-Slave controller */
126 #define SYS_RST_I2CM BIT(1) /* Reset I2C-Master controller */
129 #define SYS_RST_DSIRX BIT(4) /* Reset DSI-RX and App controller */
136 /* Lane enable PPI and DSI register bits */
[all …]
/linux-5.10/arch/arm64/boot/dts/nvidia/
Dtegra210-p2371-2180.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra210-p2180.dtsi"
5 #include "tegra210-p2597.dtsi"
9 compatible = "nvidia,p2371-2180", "nvidia,tegra210";
14 avdd-pll-uerefe-supply = <&avdd_1v05_pll>;
15 hvddio-pex-supply = <&vdd_1v8>;
16 dvddio-pex-supply = <&vdd_pex_1v05>;
17 dvdd-pex-pll-supply = <&vdd_pex_1v05>;
18 hvdd-pex-pll-e-supply = <&vdd_1v8>;
[all …]
/linux-5.10/arch/arm/boot/dts/
Dstm32mp157c-ev1.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 /dts-v1/;
8 #include "stm32mp157c-ed1.dts"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
14 compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157";
17 stdout-path = "serial0:115200n8";
27 clk_ext_camera: clk-ext-camera {
28 #clock-cells = <0>;
[all …]
Dstm32mp157c-dk2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
7 /dts-v1/;
11 #include "stm32mp15-pinctrl.dtsi"
12 #include "stm32mp15xxac-pinctrl.dtsi"
13 #include "stm32mp15xx-dkx.dtsi"
16 model = "STMicroelectronics STM32MP157C-DK2 Discovery Board";
17 compatible = "st,stm32mp157c-dk2", "st,stm32mp157";
28 stdout-path = "serial0:115200n8";
32 &dsi {
[all …]
Dqcom-msm8974.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interconnect/qcom,msm8974.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
10 #include <dt-bindings/gpio/gpio.h>
13 #address-cells = <1>;
[all …]
Dqcom-msm8974-lge-nexus5-hammerhead.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include "qcom-msm8974.dtsi"
3 #include "qcom-pm8841.dtsi"
4 #include "qcom-pm8941.dtsi"
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
19 stdout-path = "serial0:115200n8";
25 pm8841-regulators {
27 regulator-min-microvolt = <675000>;
[all …]
/linux-5.10/arch/arm64/boot/dts/qcom/
Dsdm845-mtp.dts1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
16 compatible = "qcom,sdm845-mtp", "qcom,sdm845";
23 stdout-path = "serial0:115200n8";
26 vph_pwr: vph-pwr-regulator {
27 compatible = "regulator-fixed";
28 regulator-name = "vph_pwr";
29 regulator-min-microvolt = <3700000>;
[all …]
/linux-5.10/Documentation/devicetree/bindings/display/rockchip/
Drockchip-lvds.txt5 - compatible: matching the soc type, one of
6 - "rockchip,rk3288-lvds";
7 - "rockchip,px30-lvds";
9 - reg: physical base address of the controller and length
11 - clocks: must include clock specifiers corresponding to entries in the
12 clock-names property.
13 - clock-names: must contain "pclk_lvds"
15 - avdd1v0-supply: regulator phandle for 1.0V analog power
16 - avdd1v8-supply: regulator phandle for 1.8V analog power
17 - avdd3v3-supply: regulator phandle for 3.3V analog power
[all …]
/linux-5.10/arch/arm64/boot/dts/allwinner/
Dsun50i-a64-nanopi-a64.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 /dts-v1/;
6 #include "sun50i-a64.dtsi"
7 #include "sun50i-a64-cpu-opp.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
13 compatible = "friendlyarm,nanopi-a64", "allwinner,sun50i-a64";
21 stdout-path = "serial0:115200n8";
24 hdmi-connector {
25 compatible = "hdmi-connector";
30 remote-endpoint = <&hdmi_out_con>;
[all …]
Dsun50i-a64-bananapi-m64.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 /dts-v1/;
6 #include "sun50i-a64.dtsi"
7 #include "sun50i-a64-cpu-opp.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
12 model = "BananaPi-M64";
13 compatible = "sinovoip,bananapi-m64", "allwinner,sun50i-a64";
22 stdout-path = "serial0:115200n8";
25 hdmi-connector {
26 compatible = "hdmi-connector";
[all …]
/linux-5.10/drivers/gpu/drm/exynos/
Dexynos_drm_dsi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung SoC MIPI DSI Master driver.
18 #include <linux/phy/phy.h>
104 #define DSIM_MAIN_VRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 16)
105 #define DSIM_MAIN_HRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 0)
264 struct phy *phy; member
321 static inline void exynos_dsi_write(struct exynos_dsi *dsi, enum reg_idx idx, in exynos_dsi_write() argument
325 writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]); in exynos_dsi_write()
328 static inline u32 exynos_dsi_read(struct exynos_dsi *dsi, enum reg_idx idx) in exynos_dsi_read() argument
330 return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]); in exynos_dsi_read()
[all …]
/linux-5.10/drivers/gpu/drm/sun4i/
Dsun6i_mipi_dsi.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2017-2018 Bootlin
11 #include <linux/crc-ccitt.h>
14 #include <linux/phy/phy-mipi-dphy.h>
15 #include <linux/phy/phy.h>
291 static void sun6i_dsi_inst_abort(struct sun6i_dsi *dsi) in sun6i_dsi_inst_abort() argument
293 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_abort()
297 static void sun6i_dsi_inst_commit(struct sun6i_dsi *dsi) in sun6i_dsi_inst_commit() argument
299 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_commit()
304 static int sun6i_dsi_inst_wait_for_completion(struct sun6i_dsi *dsi) in sun6i_dsi_inst_wait_for_completion() argument
[all …]
/linux-5.10/drivers/gpu/drm/msm/dsi/phy/
Ddsi_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
11 (((n) >= 0) ? (((n) + (d) - 1) / (d)) : (((n) - (d) + 1) / (d)))
18 v = (tmax - tmin) * percent; in linear_inter()
21 return max_t(s32, min_result, v - 1); in linear_inter()
33 temp = 300 * coeff - ((timing->clk_prepare >> 1) + 1) * 2 * ui; in dsi_dphy_timing_calc_clk_zero()
34 tmin = S_DIV_ROUND_UP(temp, ui) - 2; in dsi_dphy_timing_calc_clk_zero()
44 temp = (timing->hs_rqst + timing->clk_prepare + clk_z) & 0x7; in dsi_dphy_timing_calc_clk_zero()
45 timing->clk_zero = clk_z + 8 - temp; in dsi_dphy_timing_calc_clk_zero()
51 const unsigned long bit_rate = clk_req->bitclk_rate; in msm_dsi_dphy_timing_calc()
52 const unsigned long esc_rate = clk_req->escclk_rate; in msm_dsi_dphy_timing_calc()
[all …]

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