Home
last modified time | relevance | path

Searched full:on (Results 2751 – 2775 of 3118) sorted by relevance

1...<<111112113114115116117118119120>>...125

/qemu/hw/arm/
H A Dstm32f405_soc.c102 * so it is correctly parented and not leaked on an init/deinit; it is not in stm32f405_soc_realize()
H A Dnpcm7xx.c424 object_property_add_alias(obj, "power-on-straps", OBJECT(&s->gcr), in npcm7xx_init()
425 "power-on-straps"); in npcm7xx_init()
H A Dnpcm8xx.c418 object_property_add_alias(obj, "power-on-straps", OBJECT(&s->gcr), in npcm8xx_init()
419 "power-on-straps"); in npcm8xx_init()
/qemu/tests/qtest/libqos/
H A Dvirtio-pci-modern.c332 * 0x103F depending on the device type" in probe_device_type()
/qemu/ui/
H A Dgtk-egl.c7 * This code handles opengl support on older gtk versions, using egl
H A Ddbus-listener.c878 int x, int y, bool on) in dbus_mouse_set() argument
883 ddl->proxy, x, y, on, G_DBUS_CALL_FLAGS_NONE, -1, NULL, NULL, NULL); in dbus_mouse_set()
/qemu/hw/watchdog/
H A Dwdt_aspeed.c269 /* Do not reset on SDRAM controller reset */ in aspeed_wdt_timer_expired()
/qemu/target/arm/tcg/
H A Dtranslate-sme.c60 * several times in a loop with an increasing offset. We rely on in get_tile_rowcol()
/qemu/linux-user/
H A Dqemu.h260 * and unlocking on the data type.
/qemu/net/
H A Dstream.c357 /* Disable Nagle algorithm on TCP sockets to reduce latency */ in net_stream_client_connected()
/qemu/hw/char/
H A Dsh_serial.c6 * Based on serial.c - QEMU 16450 UART emulation
/qemu/scripts/tracetool/
H A D__init__.py325 # Star matching on PRI is dangerous as one might have multiple
/qemu/hw/vfio-user/
H A Ddevice.c118 * longer rely on the sequential nature of vfio-user request handling to in vfio_user_get_region_info()
H A Dpci.c364 * QEMU_PCI_CAP_EXPRESS initialization does not depend on QEMU command in vfio_user_instance_init()
/qemu/disas/
H A Dm68k.c274 a three bit register offset, depending on the field type.
411 (aka Access Control reg 0 -- AC0 -- on 68ec030)
413 (aka Access Control reg 1 -- AC1 -- on 68ec030)
431 Y PSR (68851) (MMUSR on 68030) (ACUSR on 68ec030)
466 The place to store depends on the magnitude of offset.
629 on error. */
955 /* Print a base register REGNO and displacement DISP, on INFO->STREAM.
1798 aren't going to print anything based on it. */ in match_insn_m68k()
1863 on INFO->STREAM. Returns length of the instruction, in bytes. */
1881 table on the upper four bits of the opcode. */ in print_insn_m68k()
[all …]
/qemu/tcg/i386/
H A Dtcg-target.c.inc156 registers on x86_64, and two random call clobbered registers on
644 whereas relying on optimization may not be able to exclude them. */
1424 * partial flags update stalls on Pentium4 and are not recommended
1771 * Relying on the carry bit, use SBB to produce -1 if LTU, 0 if GEU.
1969 * argument before the call but rely on the normal store to the
2386 * use VMOVDQU on the unaligned nonatomic path for simplicity.
2540 * use VMOVDQU on the unaligned nonatomic path for simplicity.
3415 * On the off-chance that we can use the high-byte registers.
/qemu/target/i386/tcg/
H A Ddecode-new.c.inc23 * The decoder is mostly based on tables copied from the Intel SDM. As
46 * For memory-only operands, if the emitter functions wants to rely on
130 * (^) these are the two cases in which Intel and AMD disagree on the
505 X86_OP_ENTRY3(MOVQ, V,x, None,None, W,q, vex5), /* wrong dest Vy on SDM! */
1342 …[0x6e] = X86_OP_ENTRY3(MOVD_to, V,x, None,None, E,y, vex5 mmx p_00_66), /* wrong dest Vy on SD…
1926 case X86_SIZE_v: /* 16/32/64-bit, based on operand size */
1940 case X86_SIZE_y: /* 32/64-bit, based on operand size */
1975 case X86_SIZE_x: /* 128/256-bit, based on operand size */
2045 * code instead, to save on hflags bits.
/qemu/hw/usb/
H A Dxen-usb.c40 * macro added we rely on.
199 * Prepare supporting those by doing the work needed on the guest in usbback_gnttab_map()
/qemu/accel/tcg/
H A Dldst_atomicity.c.inc464 * but it's trivially supported on all hosts, better than 4
724 * As store_bytes_leN, but atomically on each aligned part.
/qemu/tests/unit/
H A Dtest-aio.c379 * an fd to wait on. Fixing this breaks other tests. So create a dummy one. in test_timer_schedule()
711 * an fd to wait on. Fixing this breaks other tests. So create a dummy one. in test_source_timer_schedule()
/qemu/hw/acpi/
H A Derst.c86 * is utilized to avoid a possible misaligned access on the host.
793 * NOTE: All actions/operations/side effects happen on the WRITE, in erst_reg_write()
/qemu/hw/ppc/
H A Dpnv_occ.c64 * OCCMISC IRQ bit triggers the interrupt on a 0->1 edge, but not clear in pnv_occ_set_misc()
580 * @gpus_present: Bitmask of GPUs present (on systems where GPU
/qemu/target/arm/
H A Dcpu-features.h38 * flavour of the register doesn't have the bit, and so on).
257 * relevant, to avoid accidentally enabling a Neon feature on
/qemu/target/i386/hvf/
H A Dhvf.c43 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
126 /* EPT fault on an instruction fetch doesn't make sense here */ in ept_emulation_fault()
/qemu/hw/virtio/
H A Dvhost.c182 * performance churn on the hot path for log scanning. Even when in vhost_dev_elect_mem_logger()
697 error_report("Verify ring failure on region %d", i); in vhost_commit()
738 * It relies on the listener calling us in memory address order
1544 " decided how many memory slots to use based on the overall" in vhost_dev_init()

1...<<111112113114115116117118119120>>...125