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/linux-5.10/Documentation/devicetree/bindings/arm/ !
Dcoresight.txt1 * CoreSight Components:
3 CoreSight components are compliant with the ARM CoreSight architecture
8 sink. Each CoreSight component device should use these properties to describe
11 * Required properties for all components *except* non-configurable replicators
12 and non-configurable funnels:
16 - Embedded Trace Buffer (version 1.0):
17 "arm,coresight-etb10", "arm,primecell";
19 - Trace Port Interface Unit:
20 "arm,coresight-tpiu", "arm,primecell";
22 - Trace Memory Controller, used for Embedded Trace Buffer(ETB),
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Dcoresight-cti.yaml1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/coresight-cti.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: ARM Coresight Cross Trigger Interface (CTI) device.
11 The CoreSight Embedded Cross Trigger (ECT) consists of CTI devices connected
12 to one or more CoreSight components and/or a CPU, with CTIs interconnected in
15 not part of the CoreSight graph described in the general CoreSight bindings
16 file coresight.txt.
38 indicate this feature (arm,coresight-cti-v8-arch).
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/linux-5.10/drivers/hwtracing/coresight/ !
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Coresight configuration
5 menuconfig CORESIGHT config
6 tristate "CoreSight Tracing Support"
12 This framework provides a kernel interface for the CoreSight debug
14 a topological view of the CoreSight components based on a DT
19 module will be called coresight.
21 if CORESIGHT
23 tristate "CoreSight Link and Sink drivers"
25 This enables support for CoreSight link and sink drivers that are
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Dcoresight-platform.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/coresight.h>
21 #include "coresight-priv.h"
29 if (pdata->nr_outport) { in coresight_alloc_conns()
30 pdata->conns = devm_kcalloc(dev, pdata->nr_outport, in coresight_alloc_conns()
31 sizeof(*pdata->conns), GFP_KERNEL); in coresight_alloc_conns()
32 if (!pdata->conns) in coresight_alloc_conns()
33 return -ENOMEM; in coresight_alloc_conns()
45 * If we have a non-configurable replicator, it will be found on the in coresight_find_device_by_fwnode()
53 * We have a configurable component - circle through the AMBA bus in coresight_find_device_by_fwnode()
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Dcoresight-cti-platform.c1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/coresight.h>
12 #include <dt-bindings/arm/coresight-cti-dt.h>
14 #include "coresight-cti.h"
15 #include "coresight-priv.h"
23 #define CTI_DT_CONNS "trig-conns"
26 #define CTI_DT_V8ARCH_COMPAT "arm,coresight-cti-v8-arch"
27 #define CTI_DT_CSDEV_ASSOC "arm,cs-dev-assoc"
28 #define CTI_DT_TRIGIN_SIGS "arm,trig-in-sigs"
29 #define CTI_DT_TRIGOUT_SIGS "arm,trig-out-sigs"
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Dcoresight-cpu-debug.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/coresight.h>
26 #include "coresight-priv.h"
66 * 0b0000 - Sample offset applies based on the instruction state, we
68 * 0b0001 - No offset applies.
69 * 0b0010 - No offset applies, but do not use in AArch32 mode
109 MODULE_PARM_DESC(enable, "Control to enable coresight CPU debug functionality");
114 writel_relaxed(0x0, drvdata->base + EDOSLAR); in debug_os_unlock()
126 * - CPU power domain is powered off;
127 * - The OS Double Lock is locked;
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Dcoresight-cti-core.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/coresight.h>
22 #include "coresight-priv.h"
23 #include "coresight-cti.h"
26 * CTI devices can be associated with a PE, or be connected to CoreSight
30 * We assume that the non-CPU CTIs are always powered as we do with sinks etc.
43 dev_get_drvdata(csdev->dev.parent)
56 * CTI device name list - for CTI not bound to cores.
60 /* write set of regs to hardware - call with spinlock claimed */
63 struct cti_config *config = &drvdata->config; in cti_write_all_hw_regs()
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Dcoresight-etm3x-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
5 * Description: CoreSight Program Flow Trace driver
24 #include <linux/coresight.h>
25 #include <linux/coresight-pmu.h>
33 #include "coresight-etm.h"
34 #include "coresight-etm-perf.h"
56 drvdata->os_unlock = true; in etm_os_unlock()
88 etmpdcr = readl_relaxed(drvdata->base + ETMPDCR); in etm_set_pwrup()
90 writel_relaxed(etmpdcr, drvdata->base + ETMPDCR); in etm_set_pwrup()
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Dcoresight-catu.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include "coresight-priv.h"
41 * AXI - ARPROT bits:
45 * Bit 0: 0 - Unprivileged access, 1 - Privileged access
46 * Bit 1: 0 - Secure access, 1 - Non-secure access.
47 * Bit 2: 0 - Data access, 1 - instruction access.
73 return coresight_read_reg_pair(drvdata->base, offset, -1); \
78 coresight_write_reg_pair(drvdata->base, val, offset, -1); \
85 return coresight_read_reg_pair(drvdata->base, lo_off, hi_off); \
90 coresight_write_reg_pair(drvdata->base, val, lo_off, hi_off); \
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Dcoresight-etm4x-core.c1 // SPDX-License-Identifier: GPL-2.0
22 #include <linux/coresight.h>
23 #include <linux/coresight-pmu.h>
35 #include "coresight-etm4x.h"
36 #include "coresight-etm-perf.h"
42 #define PARAM_PM_SAVE_FIRMWARE 0 /* save self-hosted state as per firmware */
44 #define PARAM_PM_SAVE_SELF_HOSTED 2 /* save self-hosted state only */
49 "Save/restore state on power down: 1 = never, 2 = self-hosted");
62 writel_relaxed(0x0, drvdata->base + TRCOSLAR); in etm4_os_unlock()
63 drvdata->os_unlock = true; in etm4_os_unlock()
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/linux-5.10/arch/arm/boot/dts/ !
Dhip04.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-2014 Hisilicon Ltd.
6 * Copyright (C) 2013-2014 Linaro Ltd.
12 /* memory bus is 64-bit */
13 #address-cells = <2>;
14 #size-cells = <2>;
21 compatible = "hisilicon,hip04-bootwrapper";
22 boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
26 #address-cells = <1>;
27 #size-cells = <0>;
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Dvexpress-v2p-ca15_a7.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
8 * HBI-0249A
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA15_CA7";
18 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
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Dqcom-apq8064.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
6 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/soc/qcom,gsbi.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #address-cells = <1>;
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Dimx7s.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 #include <dt-bindings/clock/imx7d-clock.h>
7 #include <dt-bindings/power/imx7-power.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/imx7-reset.h>
12 #include "imx7d-pinfunc.h"
15 #address-cells = <1>;
16 #size-cells = <1>;
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Dimx7d.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
7 #include <dt-bindings/reset/imx7-reset.h>
12 clock-frequency = <996000000>;
13 operating-points-v2 = <&cpu0_opp_table>;
14 #cooling-cells = <2>;
15 nvmem-cells = <&fuse_grade>;
16 nvmem-cell-names = "speed_grade";
20 compatible = "arm,cortex-a7";
23 clock-frequency = <996000000>;
24 operating-points-v2 = <&cpu0_opp_table>;
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/linux-5.10/Documentation/trace/coresight/ !
Dcoresight-cpu-debug.rst2 Coresight CPU Debug Module
9 ------------
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
13 debug module and it is mainly used for two modes: self-hosted debug and
16 explore debugging method which rely on self-hosted debug mode, this document
19 The debug module provides sample-based profiling extension, which can be used
21 every CPU has one dedicated debug module to be connected. Based on self-hosted
29 --------------
31 - During driver registration, it uses EDDEVID and EDDEVID1 - two device ID
32 registers to decide if sample-based profiling is implemented or not. On some
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Dcoresight-ect.rst1 .. SPDX-License-Identifier: GPL-2.0
4 CoreSight Embedded Cross Trigger (CTI & CTM).
11 --------------------
13 The CoreSight Cross Trigger Interface (CTI) is a hardware device that takes
21 0 C 0----------->: : +======>(other CTI channel IO)
22 0 P 0<-----------: : v
24 0000000 : CTI :<=========>*CTM*<====>: CTI :---+
25 ####### in_trigs : : (id 0-3) ***** ::::::: v
26 # ETM #----------->: : ^ #######
27 # #<-----------: : +---# ETR #
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Dcoresight.rst2 Coresight - HW Assisted Tracing on ARM
9 ------------
11 Coresight is an umbrella of technologies allowing for the debugging of ARM
24 flows through the coresight system (via ATB bus) using links that are connecting
25 the emanating source to a sink(s). Sinks serve as endpoints to the coresight
28 host without fear of filling up the onboard coresight memory buffer.
30 At typical coresight system would look like this::
38 0 CPU 0<-->: C : 0 CPU 0<-->: C : : C : @ STM @ || System ||
39 |->0000000 : T : |->0000000 : T : : T :<--->@@@@@ || Memory ||
40 | #######<-->: I : | #######<-->: I : : I : @@@<-| ||||||||||||
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/linux-5.10/Documentation/ABI/testing/ !
Dsysfs-bus-coresight-devices-etm4x1 What: /sys/bus/coresight/devices/etm<N>/enable_source
8 of coresight components linking the source to the sink is
9 configured and managed automatically by the coresight framework.
11 What: /sys/bus/coresight/devices/etm<N>/cpu
17 What: /sys/bus/coresight/devices/etm<N>/nr_pe_cmp
24 What: /sys/bus/coresight/devices/etm<N>/nr_addr_cmp
31 What: /sys/bus/coresight/devices/etm<N>/nr_cntr
38 What: /sys/bus/coresight/devices/etm<N>/nr_ext_inp
44 What: /sys/bus/coresight/devices/etm<N>/numcidc
51 What: /sys/bus/coresight/devices/etm<N>/numvmidc
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/linux-5.10/arch/arm64/boot/dts/sprd/ !
Dsc9863a.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/clock/sprd,sc9863a-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #address-cells = <2>;
15 #size-cells = <0>;
17 cpu-map {
48 compatible = "arm,cortex-a55";
50 enable-method = "psci";
51 cpu-idle-states = <&CORE_PD>;
56 compatible = "arm,cortex-a55";
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/linux-5.10/arch/arm64/boot/dts/qcom/ !
Dmsm8916.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/arm/coresight-cti-dt.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/interconnect/qcom,msm8916.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
12 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&intc>;
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Dsc7180.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
15 #include <dt-bindings/interconnect/qcom,sc7180.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
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/linux-5.10/tools/perf/util/ !
Dcs-etm.h1 /* SPDX-License-Identifier: GPL-2.0 */
21 /* PMU->type (32 bit), total # of CPUs (32 bit) */
61 * table 7-12 Encoding of Exception[3:0] for non-ARMv7-M processors.
83 * table 6-12 Possible values for the TYPE field in an Exception instruction
84 * trace packet, for ARMv7-A/R and ARMv8-A/R PEs.
139 * When working with per-thread scenarios the process under trace can
142 * as per the CoreSight architecture, use that specific value to
188 return -1; in cs_etm__process_auxtrace_info()
194 return -1; in cs_etm__get_cpu()
202 return -1; in cs_etm__etmq_set_tid()
/linux-5.10/tools/perf/ !
Dcheck-headers.sh2 # SPDX-License-Identifier: GPL-2.0
30 arch/x86/include/asm/disabled-features.h
31 arch/x86/include/asm/required-features.h
36 arch/x86/include/asm/msr-index.h
38 arch/x86/lib/x86-opcode-map.txt
39 arch/x86/tools/gen-insn-attr-x86.awk
65 include/asm-generic/bitops/arch_hweight.h
66 include/asm-generic/bitops/const_hweight.h
67 include/asm-generic/bitops/__fls.h
68 include/asm-generic/bitops/fls.h
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/linux-5.10/tools/perf/Documentation/ !
Dperf-list.txt1 perf-list(1)
5 ----
6 perf-list - List all symbolic event types
9 --------
11 'perf list' [--no-desc] [--long-desc]
15 -----------
17 various perf commands with the -e option.
20 -------
21 -d::
22 --desc::
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