Lines Matching +full:non +full:- +full:coresight

1 * CoreSight Components:
3 CoreSight components are compliant with the ARM CoreSight architecture
8 sink. Each CoreSight component device should use these properties to describe
11 * Required properties for all components *except* non-configurable replicators
12 and non-configurable funnels:
16 - Embedded Trace Buffer (version 1.0):
17 "arm,coresight-etb10", "arm,primecell";
19 - Trace Port Interface Unit:
20 "arm,coresight-tpiu", "arm,primecell";
22 - Trace Memory Controller, used for Embedded Trace Buffer(ETB),
26 "arm,coresight-tmc", "arm,primecell";
28 - Trace Programmable Funnel:
29 "arm,coresight-dynamic-funnel", "arm,primecell";
30 "arm,coresight-funnel", "arm,primecell"; (OBSOLETE. For
33 - Embedded Trace Macrocell (version 3.x) and
35 "arm,coresight-etm3x", "arm,primecell";
37 - Embedded Trace Macrocell (version 4.x):
38 "arm,coresight-etm4x", "arm,primecell";
40 - Coresight programmable Replicator :
41 "arm,coresight-dynamic-replicator", "arm,primecell";
43 - System Trace Macrocell:
44 "arm,coresight-stm", "arm,primecell"; [1]
45 - Coresight Address Translation Unit (CATU)
46 "arm,coresight-catu", "arm,primecell";
48 - Coresight Cross Trigger Interface (CTI):
49 "arm,coresight-cti", "arm,primecell";
50 See coresight-cti.yaml for full CTI definitions.
57 * clock-names: the name of the clocks referenced by the code.
60 coresight blocks also have an additional clock "atclk", which
61 clocks the core of that coresight component. The latter clock
64 * port or ports: see "Graph bindings for Coresight" below.
76 * reg-names: the only acceptable values are "stm-base" and
77 "stm-stimulus-base", each corresponding to the areas defined in "reg".
79 * Required properties for Coresight Cross Trigger Interface (CTI)
80 See coresight-cti.yaml for full CTI definitions.
83 non-configurable replicators and non-configurable funnels:
87 - Coresight Non-configurable Replicator:
88 "arm,coresight-static-replicator";
89 "arm,coresight-replicator"; (OBSOLETE. For backward
92 - Coresight Non-configurable Funnel:
93 "arm,coresight-static-funnel";
95 * port or ports: see "Graph bindings for Coresight" below.
99 * arm,coresight-loses-context-with-cpu : boolean. Indicates that the
102 coresight component and CPU in the same power domain. When the CPU
103 powers down the coresight component also powers down and loses its
109 registers via co-processor 14.
111 * qcom,skip-power-up: boolean. Indicates that an implementation can
120 * arm,buffer-size: size of contiguous buffer space for TMC ETR
124 * arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely
133 * qcom,replicator-loses-context: boolean. Indicates that the replicator
137 Graph bindings for Coresight
138 -------------------------------
140 Coresight components are interconnected to create a data path for the flow of
142 Each coresight component must describe the "input" and "output" connections.
147 * All output ports must be listed inside a child node named "out-ports"
148 * All input ports must be listed inside a child node named "in-ports".
155 compatible = "arm,coresight-etb10", "arm,primecell";
159 clock-names = "apb_pclk";
160 in-ports {
163 remote-endpoint = <&replicator_out_port0>;
170 compatible = "arm,coresight-tpiu", "arm,primecell";
174 clock-names = "apb_pclk";
175 in-ports {
178 remote-endpoint = <&replicator_out_port1>;
185 compatible = "arm,coresight-tmc", "arm,primecell";
189 clock-names = "apb_pclk";
190 in-ports {
193 remote-endpoint = <&replicator2_out_port0>;
198 out-ports {
201 remote-endpoint = <&catu_in_port>;
209 /* non-configurable replicators don't show up on the
212 compatible = "arm,coresight-static-replicator";
214 out-ports {
215 #address-cells = <1>;
216 #size-cells = <0>;
222 remote-endpoint = <&etb_in_port>;
229 remote-endpoint = <&tpiu_in_port>;
234 in-ports {
237 remote-endpoint = <&funnel_out_port0>;
245 * non-configurable funnel don't show up on the AMBA
248 compatible = "arm,coresight-static-funnel";
250 clock-names = "apb_pclk";
252 out-ports {
255 remote-endpoint = <&top_funnel_in>;
260 in-ports {
261 #address-cells = <1>;
262 #size-cells = <0>;
267 remote-endpoint = <&cluster0_etf_out>;
274 remote-endpoint = <&cluster1_etf_out>;
281 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
285 clock-names = "apb_pclk";
286 out-ports {
289 remote-endpoint =
295 in-ports {
296 #address-cells = <1>;
297 #size-cells = <0>;
302 remote-endpoint = <&ptm0_out_port>;
309 remote-endpoint = <&ptm1_out_port>;
316 remote-endpoint = <&etm0_out_port>;
325 compatible = "arm,coresight-etm3x", "arm,primecell";
330 clock-names = "apb_pclk";
331 out-ports {
334 remote-endpoint = <&funnel_in_port0>;
341 compatible = "arm,coresight-etm3x", "arm,primecell";
346 clock-names = "apb_pclk";
347 out-ports {
350 remote-endpoint = <&funnel_in_port1>;
358 compatible = "arm,coresight-stm", "arm,primecell";
361 reg-names = "stm-base", "stm-stimulus-base";
364 clock-names = "apb_pclk";
365 out-ports {
368 remote-endpoint = <&main_funnel_in_port2>;
377 compatible = "arm,coresight-catu", "arm,primecell";
381 clock-names = "apb_pclk";
384 in-ports {
387 remote-endpoint = <&etr_out_port>;