perf/Documentation/perf-list.txt

1 perf-list(1)
5 ----
6 perf-list - List all symbolic event types
9 --------
11 'perf list' [--no-desc] [--long-desc]
15 -----------
17 various perf commands with the -e option.
20 -------
21 -d::
22 --desc::
25 --no-desc::
28 -v::
29 --long-desc::
32 --debug::
35 --details::
39 --deprecated::
44 ---------------
50  u - user-space counting
51  k - kernel counting
52  h - hypervisor counting
53  I - non idle counting
54  G - guest counting (in KVM guests)
55  H - host counting (not in KVM guests)
56  p - precise level
57  P - use maximum detected precise level
58  S - read sample value (PERF_SAMPLE_READ)
59  D - pin the event to the PMU
60  W - group is weak and will fallback to non-group if not schedulable,
61  e - group or event are exclusive and do not share the PMU
66  0 - SAMPLE_IP can have arbitrary skid
67  1 - SAMPLE_IP must have constant skid
68  2 - SAMPLE_IP requested to have 0 skid
69  3 - SAMPLE_IP must have 0 skid, or uses randomization to avoid
73 which supports up to precise-level 2, and precise level 3 for
76 On AMD systems it is implemented using IBS (up to precise-level 2).
77 The precise modifier works with event types 0x76 (cpu-cycles, CPU
78 clocks not halted) and 0xC1 (micro-ops retired). Both events map to
81 Manual Volume 2: System Programming, 13.3 Instruction-Based
84  perf record -a -e cpu-cycles:p ...    # use ibs op counting cycles
85  perf record -a -e r076:p ...          # same as -e cpu-cycles:p
86  perf record -a -e r0C1:p ...          # use ibs op counting micro-ops
89 -----------------------------
94 …Lx MSRs (see [Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Prog…
96 Figure 13-7 Performance Event-Select Register (PerfEvtSeln)).
110   A8H      01H  LSD.UOPS    Counts the number of micro-ops     Use cmask=1 and
116  perf stat -e r1a8 -a sleep 1
117  perf record -e r1a8 ...
121  perf record -e r1a8 -a sleep 1
122  perf record -e cpu/r1a8/ ...
123  perf record -e cpu/r0x1a8/ ...
129 --------------
142   perf stat -e cpu/event=0xa8,umask=0x1,name=LSD.UOPS_CYCLES,cmask=0x1/ ...
146   perf stat -e cpu/event=0xa8,umask=0x1,cmask=0x1,name=\'LSD.UOPS_CYCLES:cmask=0x1\'/ ...
149 ---------------
153 with perf stat -a. They can be bound to one logical CPU, but will measure
159   perf stat -C 0 -a uncore_imc_0/cas_count_read/,uncore_imc_0/cas_count_write/ -I 1000 ...
168   perf stat -C 0 -a imc/cas_count_read/,imc/cas_count_write/ -I 1000 ...
169   perf stat -C 0 -a *imc*/cas_count_read/,*imc*/cas_count_write/ -I 1000 ...
173   perf stat -I 1000 -e power/energy-cores/  -a
176 -------------------
178 For non root users generally only context switched PMU events are available.
186 sysctl to -1, which allows non root to use these events.
193 -------
197 intel-pt.txt document.
200 --------------------
202 Some pmu events listed by 'perf-list' will be displayed with '?' in them. For
210   perf stat -C 0 -e 'hv_gpci/dtbp_ptitc,phys_processor_idx=0x2/' ...
221   perf stat -e cpu/event=0,umask=0x3,percore=1/
225 ------------
236   perf stat -e '{instructions,cycles}' ...
242 ref-cycles. Some special events have restrictions on which counter they
257 ---------------
261   perf record -e '{cycles,instructions}:S' ...
262   perf report --group
268 However, in the case AUX area events (e.g. Intel PT or CoreSight), the AUX
272 -------
278 . 'hw' or 'hardware' to list hardware events such as cache-misses, etc.
282 . 'cache' or 'hwcache' to list hardware cache events such as L1-dcache-loads, etc.
306 . '--raw-dump', shows the raw-dump of all the events.
307 . '--raw-dump [hw|sw|cache|tracepoint|pmu|event_glob]', shows the raw-dump of
311 --------
312 linkperf:perf-stat[1], linkperf:perf-top[1],
313 linkperf:perf-record[1],
314 http://www.intel.com/sdm/[Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: …