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/linux-6.15/tools/perf/pmu-events/arch/x86/amdzen4/
Dfloating-point.json5 "BriefDescription": "Retired x87 floating-point add and subtract ops.",
11 "BriefDescription": "Retired x87 floating-point multiply ops.",
17 "BriefDescription": "Retired x87 floating-point divide and square root ops.",
23 "BriefDescription": "Retired x87 floating-point ops of all types.",
29 "BriefDescription": "Retired SSE and AVX floating-point add and subtract ops.",
35 "BriefDescription": "Retired SSE and AVX floating-point multiply ops.",
41 "BriefDescription": "Retired SSE and AVX floating-point divide and square root ops.",
47 …"BriefDescription": "Retired SSE and AVX floating-point multiply-accumulate ops (each operation is…
53 …"BriefDescription": "Retired SSE and AVX floating-point bfloat multiply-accumulate ops (each opera…
59 "BriefDescription": "Retired SSE and AVX floating-point ops of all types.",
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/linux-6.15/tools/perf/pmu-events/arch/x86/amdzen5/
Dfloating-point.json5 "BriefDescription": "Retired x87 floating-point add and subtract ops.",
11 "BriefDescription": "Retired x87 floating-point multiply ops.",
17 "BriefDescription": "Retired x87 floating-point divide and square root ops.",
23 "BriefDescription": "Retired x87 floating-point ops of all types.",
29 "BriefDescription": "Retired SSE and AVX floating-point add and subtract ops.",
35 "BriefDescription": "Retired SSE and AVX floating-point multiply ops.",
41 "BriefDescription": "Retired SSE and AVX floating-point divide and square root ops.",
47 …"BriefDescription": "Retired SSE and AVX floating-point multiply-accumulate ops (each operation is…
53 "BriefDescription": "Retired SSE and AVX floating-point bfloat16 ops.",
59 "BriefDescription": "Retired SSE and AVX floating-point scalar single-precision ops.",
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/linux-6.15/arch/arm/probes/
Ddecode-arm.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * arch/arm/probes/decode-arm.c
6 * Some code moved here from arch/arm/kernel/kprobes-arm.c
17 #include "decode-arm.h"
19 #define sign_extend(x, signbit) ((x) | (0 - ((x) & (1 << (signbit)))))
24 * To avoid the complications of mimicing single-stepping on a
25 * processor without a Next-PC or a single-step mode, and to
26 * avoid having to deal with the side-effects of boosting, we
56 long iaddr = (long) regs->ARM_pc - 4; in simulate_bbl()
60 regs->ARM_lr = iaddr + 4; in simulate_bbl()
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Ddecode-thumb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/probes/decode-thumb.c
13 #include "decode-thumb.h"
74 /* Data-processing (shifted register) */
134 /* Data-processing (modified immediate) */
186 /* Data-processing (plain binary immediate) */
389 /* Data-processing (register) */
491 /* Multiply, multiply accumulate, and absolute difference */
530 /* Long multiply, long multiply accumulate, and divide */
567 * Data-processing (shifted register)
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/linux-6.15/arch/arm/crypto/
Dnh-neon-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * NH - ε-almost-universal hash function, NEON accelerated version
63 // Multiply 32x32 => 64 and accumulate
114 vst1.8 {T0-T1}, [HASH]
Dpoly1305-armv4.pl2 # SPDX-License-Identifier: GPL-1.0+ OR BSD-3-Clause
5 # Written by Andy Polyakov, @dot-asm, initially for the OpenSSL
9 # IALU(*)/gcc-4.4 NEON
11 # ARM11xx(ARMv6) 7.78/+100% -
12 # Cortex-A5 6.35/+130% 3.00
13 # Cortex-A8 6.25/+115% 2.36
14 # Cortex-A9 5.10/+95% 2.55
15 # Cortex-A15 3.85/+85% 1.25(**)
18 # (*) this is for -march=armv6, i.e. with bunch of ldrb loading data;
19 # (**) these are trade-off results, they can be improved by ~8% but at
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/linux-6.15/arch/x86/crypto/
Dnh-sse2-x86_64.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * NH - ε-almost-universal hash function, x86_64 SSE2 accelerated
50 // Multiply 32x32 => 64 and accumulate
Dnh-avx2-x86_64.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * NH - ε-almost-universal hash function, x86_64 AVX2 accelerated
48 // Multiply 32x32 => 64 and accumulate
Dpoly1305-x86_64-cryptogams.pl2 # SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
4 # Copyright (C) 2017-2018 Samuel Neves <sneves@dei.uc.pt>. All Rights Reserved.
5 # Copyright (C) 2017-2019 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
6 # Copyright (C) 2006-2017 CRYPTOGAMS by <appro@openssl.org>. All Rights Reserved.
35 # Skylake-X system performance. Since we are likely to suppress
36 # AVX512F capability flag [at least on Skylake-X], conversion serves
43 # IALU/gcc-4.8(*) AVX(**) AVX2 AVX-512
44 # P4 4.46/+120% -
45 # Core 2 2.41/+90% -
46 # Westmere 1.88/+120% -
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/linux-6.15/arch/arm64/crypto/
Dnh-neon-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * NH - ε-almost-universal hash function, ARM64 NEON accelerated version
49 // Multiply 32x32 => 64 and accumulate
Dpoly1305-armv8.pl2 # SPDX-License-Identifier: GPL-1.0+ OR BSD-3-Clause
5 # Written by Andy Polyakov, @dot-asm, initially for the OpenSSL
15 # IALU/gcc-4.9 NEON
18 # Cortex-A53 2.69/+58% 1.47
19 # Cortex-A57 2.70/+7% 1.14
21 # X-Gene 2.13/+68% 2.27
35 ( $xlate="${dir}arm-xlate.pl" and -f $xlate ) or
36 ( $xlate="${dir}../../perlasm/arm-xlate.pl" and -f $xlate) or
37 die "can't locate arm-xlate.pl";
85 and $s1,$s1,#-4
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/linux-6.15/arch/arc/kernel/
Dhead.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
8 * -Check if we are running on Simulator or on real hardware
13 #include <asm/asm-offsets.h>
17 #include <asm/dsp-impl.h>
25 ; Disable I-cache/D-cache if kernel so configured
30 bclr r5, r5, 0 ; 0 - Enable, 1 is Disable
51 ; Unaligned access is disabled at reset, so re-enable early as
86 ; Config DSP_CTRL properly, so kernel may use integer multiply,
87 ; multiply-accumulate, and divide operations
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/linux-6.15/tools/perf/pmu-events/arch/x86/amdzen3/
Dfloating-point.json6 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
13 … Each increment represents a one-cycle dispatch event. This event is a speculative event. Since th…
20 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
27 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
34 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
40 …"BriefDescription": "All FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS.…
46 …"BriefDescription": "Multiply-Accumulate FLOPs. Each MAC operation is counted as 2 FLOPS. This is …
52 …"BriefDescription": "Divide/square root FLOPs. This is a retire-based event. The number of retired…
58 …"BriefDescription": "Multiply FLOPs. This is a retire-based event. The number of retired SSE/AVX F…
64 …"BriefDescription": "Add/subtract FLOPs. This is a retire-based event. The number of retired SSE/A…
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/linux-6.15/Documentation/devicetree/bindings/riscv/
Dextensions.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
36 Identifies the specific RISC-V instruction set architecture
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/linux-6.15/arch/s390/include/asm/
Dfpu-insn-asm.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 #error only <asm/fpu-insn.h> can be included directly
23 /* GR_NUM - Retrieve general-purpose register number
83 /* VX_NUM - Retrieve vector register number
195 /* RXB - Compute most significant bit used vector registers
200 * are stored in instruction bits 8-11.
203 * are stored in instruction bits 12-15.
206 * are stored in instruction bits 16-19.
209 * are stored in instruction bits 32-35.
213 * not limited to the vector instruction formats VRR-g, VRR-h, VRS-a, VRS-d,
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/linux-6.15/arch/arm/probes/kprobes/
Dtest-thumb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/probes/kprobes/test-thumb.c
13 #include "test-core.h"
89 TEST_GROUP("16-bit Thumb data-processing instructions") in kprobe_thumb16_test_cases()
118 TEST_R( "add sp" ", r",8,-8, "") in kprobe_thumb16_test_cases()
120 TEST_BF_R("add pc" ", r",0,2f-1f-8,"") in kprobe_thumb16_test_cases()
125 TEST_R( "cmp sp" ", r",8,-8, "") in kprobe_thumb16_test_cases()
130 TEST_P( "mov sp, r",8,-8, "") in kprobe_thumb16_test_cases()
164 TEST_GROUP("16-bit Thumb Load/store instructions") in kprobe_thumb16_test_cases()
204 TEST_GROUP("Generate PC-/SP-relative address") in kprobe_thumb16_test_cases()
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Dtest-arm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/kernel/kprobes-test-arm.c
14 #include "test-core.h"
55 TEST_GROUP("Data-processing (register), (register-shifted register), (immediate)") in kprobe_arm_test_cases()
155 /* Data-processing with PC and a shift count in a register */ in kprobe_arm_test_cases()
167 /* Data-processing with PC as a target and status registers updated */ in kprobe_arm_test_cases()
175 /* Data-processing with SP as target */ in kprobe_arm_test_cases()
185 /* Data-processing with PC as target */ in kprobe_arm_test_cases()
186 TEST_BF( "add pc, pc, #2f-1b-8") in kprobe_arm_test_cases()
187 TEST_BF_R ("add pc, pc, r",14,2f-1f-8,"") in kprobe_arm_test_cases()
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/linux-6.15/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
Dampdu.c52 #define NUM_FFPLD_FIFO 4 /* number of fifo concerned by pre-loading */
60 * accumulate between resets.
76 #define MODADD_POW2(x, y, bound) (((x) + (y)) & ((bound) - 1))
77 #define MODSUB_POW2(x, y, bound) (((x) - (y)) & ((bound) - 1))
79 /* structure to hold tx fifo information and pre-loading state
85 * ampdu_pld_size: number of bytes to be pre-loaded
86 * mcs2ampdu_table: per-mcs max # of mpdus in an ampdu
107 * ini_enable: per-tid initiator enable/disable of ampdu
112 * retry_limit_tid: per-tid mpdu transmit retry limit
113 * rr_retry_limit_tid: per-tid mpdu transmit retry limit at regular rate
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/linux-6.15/drivers/net/ethernet/chelsio/cxgb3/
Dcommon.h2 * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
44 #define CH_ERR(adap, fmt, ...) dev_err(&adap->pdev->dev, fmt, ##__VA_ARGS__)
45 #define CH_WARN(adap, fmt, ...) dev_warn(&adap->pdev->dev, fmt, ##__VA_ARGS__)
46 #define CH_ALERT(adap, fmt, ...) dev_alert(&adap->pdev->dev, fmt, ##__VA_ARGS__)
53 if ((adapter)->msg_enable & NETIF_MSG_##category) \
54 dev_printk(KERN_##level, &adapter->pdev->dev, fmt, \
92 enum { /* adapter interrupt-maintained statistics */
151 #define WR_FLITS (TX_DESC_FLITS + 1 - SGE_NUM_GENBITS)
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/linux-6.15/drivers/usb/core/
Dhub.c1 // SPDX-License-Identifier: GPL-2.0
71 /* Protect struct usb_device->state and ->children members
72 * Note: Both are also protected by ->dev.sem, except that ->state can
80 /* synchronize hub-port add/remove and peering operations */
90 * 10 seconds to send reply for the initial 64-byte descriptor request.
92 /* define initial 64-byte descriptor request timeout in milliseconds */
96 "initial 64-byte descriptor request timeout in milliseconds "
97 "(default 5000 - 5.0 seconds)");
141 if (hub_is_superspeedplus(hub->hdev)) in portspeed()
143 if (hub_is_superspeed(hub->hdev)) in portspeed()
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/linux-6.15/drivers/net/ethernet/intel/e1000e/
Dnetdev.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
36 static int debug = -1;
112 * __ew32_prepare - prepare to write to MAC CSR register on certain parts
127 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i) in __ew32_prepare()
133 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) in __ew32()
136 writel(val, hw->hw_addr + reg); in __ew32()
140 * e1000_regdump - register printout routine
150 switch (reginfo->ofs) { in e1000_regdump()
164 pr_info("%-15s %08x\n", in e1000_regdump()
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/linux-6.15/arch/x86/kvm/
Dx86.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
16 * Ben-Ami Yassour <benami@il.ibm.com>
48 #include <linux/user-return-notifier.h>
62 #include <linux/entry-kvm.h>
109 ((struct kvm_vcpu *)(ctxt)->vcpu)
112 * - enable syscall per default because its emulated by KVM
113 * - enable LME and LMA per default on 64 bit KVM
144 *(((struct kvm_x86_ops *)0)->func));
147 #include <asm/kvm-x86-ops.h>
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