arm/probes/decode-arm.c

1 // SPDX-License-Identifier: GPL-2.0-only
4  * arch/arm/probes/decode-arm.c
6  * Some code moved here from arch/arm/kernel/kprobes-arm.c
17 #include "decode-arm.h"
19 #define sign_extend(x, signbit) ((x) | (0 - ((x) & (1 << (signbit)))))
24  * To avoid the complications of mimicing single-stepping on a
25  * processor without a Next-PC or a single-step mode, and to
26  * avoid having to deal with the side-effects of boosting, we
56 	long iaddr = (long) regs->ARM_pc - 4;  in simulate_bbl()
60 		regs->ARM_lr = iaddr + 4;  in simulate_bbl()
62 	regs->ARM_pc = iaddr + 8 + disp;  in simulate_bbl()
68 	long iaddr = (long) regs->ARM_pc - 4;  in simulate_blx1()
71 	regs->ARM_lr = iaddr + 4;  in simulate_blx1()
72 	regs->ARM_pc = iaddr + 8 + disp + ((insn >> 23) & 0x2);  in simulate_blx1()
73 	regs->ARM_cpsr |= PSR_T_BIT;  in simulate_blx1()
80 	long rmv = regs->uregs[rm];  in simulate_blx2bx()
83 		regs->ARM_lr = (long) regs->ARM_pc;  in simulate_blx2bx()
85 	regs->ARM_pc = rmv & ~0x1;  in simulate_blx2bx()
86 	regs->ARM_cpsr &= ~PSR_T_BIT;  in simulate_blx2bx()
88 		regs->ARM_cpsr |= PSR_T_BIT;  in simulate_blx2bx()
96 	regs->uregs[rd] = regs->ARM_cpsr & mask;  in simulate_mrs()
102 	regs->uregs[12] = regs->uregs[13];  in simulate_mov_ipsp()
186 	/* Halfword multiply and multiply-accumulate			*/
208 	/* Multiply and multiply-accumulate				*/
299 	/* Data-processing (register)					*/
332 	/* TST (reg-shift reg)	cccc 0001 0001 xxxx xxxx xxxx 0xx1 xxxx */
333 	/* TEQ (reg-shift reg)	cccc 0001 0011 xxxx xxxx xxxx 0xx1 xxxx */
334 	/* CMP (reg-shift reg)	cccc 0001 0101 xxxx xxxx xxxx 0xx1 xxxx */
335 	/* CMN (reg-shift reg)	cccc 0001 0111 xxxx xxxx xxxx 0xx1 xxxx */
339 	/* MOV (reg-shift reg)	cccc 0001 101x xxxx xxxx xxxx 0xx1 xxxx */
340 	/* MVN (reg-shift reg)	cccc 0001 111x xxxx xxxx xxxx 0xx1 xxxx */
344 	/* AND (reg-shift reg)	cccc 0000 000x xxxx xxxx xxxx 0xx1 xxxx */
345 	/* EOR (reg-shift reg)	cccc 0000 001x xxxx xxxx xxxx 0xx1 xxxx */
346 	/* SUB (reg-shift reg)	cccc 0000 010x xxxx xxxx xxxx 0xx1 xxxx */
347 	/* RSB (reg-shift reg)	cccc 0000 011x xxxx xxxx xxxx 0xx1 xxxx */
348 	/* ADD (reg-shift reg)	cccc 0000 100x xxxx xxxx xxxx 0xx1 xxxx */
349 	/* ADC (reg-shift reg)	cccc 0000 101x xxxx xxxx xxxx 0xx1 xxxx */
350 	/* SBC (reg-shift reg)	cccc 0000 110x xxxx xxxx xxxx 0xx1 xxxx */
351 	/* RSC (reg-shift reg)	cccc 0000 111x xxxx xxxx xxxx 0xx1 xxxx */
352 	/* ORR (reg-shift reg)	cccc 0001 100x xxxx xxxx xxxx 0xx1 xxxx */
353 	/* BIC (reg-shift reg)	cccc 0001 110x xxxx xxxx xxxx 0xx1 xxxx */
361 	/* Data-processing (immediate)					*/
620 	 * Halfword multiply and multiply-accumulate
626 	 * Multiply and multiply-accumulate
644 	 * Data-processing (register)
646 	 * Data-processing (register-shifted register)
652 	 * Data-processing (immediate)
703 	regs->ARM_pc += 4;  in arm_singlestep()
704 	asi->insn_handler(insn, asi, regs);  in arm_singlestep()
724 	asi->insn_singlestep = arm_singlestep;  in arm_probes_decode_insn()
725 	asi->insn_check_cc = probes_condition_checks[insn>>28];  in arm_probes_decode_insn()