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/kvm-unit-tests/x86/
H A Dmsr.c1 /* msr tests */
6 #include "msr.h"
12 * 2. Custom: by providing command line arguments it is possible to test any MSR and value
14 * 1. msr index as a base 16 number
30 #define MSR_TEST(msr, val, ro) \ argument
31 { .index = msr, .name = #msr, .value = val, .is_64bit_only = false, .keep = ro }
32 #define MSR_TEST_ONLY64(msr, val, ro) \ argument
33 { .index = msr, .name = #msr, .value = val, .is_64bit_only = true, .keep = ro }
55 static void __test_msr_rw(u32 msr, const char *name, unsigned long long val, in __test_msr_rw() argument
60 orig = rdmsr(msr); in __test_msr_rw()
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H A DREADME10 These invocations run the msr test case and outputs to stdio.
15 -chardev file,id=testlog,path=msr.out \
16 -serial stdio -kernel ./x86/msr.flat
22 -kernel ./x86/msr.flat
29 msr: write to msr (only KERNEL_GS_BASE for now)
H A Dtsc_adjust.c14 "MSR_IA32_TSC_ADJUST msr initialization"); in main()
20 "MSR_IA32_TSC_ADJUST msr read / write"); in main()
26 "MSR_IA32_TSC_ADJUST msr read / write"); in main()
H A Dla57.c4 #include "msr.h"
14 TEST_REGISTER_MSR /* upper 32 bits = msr address */
20 u32 msr = test_register >> 32; in get_test_register_value() local
39 return rdmsr(msr); in get_test_register_value()
55 u32 msr = test_register >> 32; in set_test_register_value() local
116 wrmsr(msr, value); in set_test_register_value()
119 return wrmsr_safe(msr, value) == 0; in set_test_register_value()
121 return wrmsr_fep_safe(msr, value) == 0; in set_test_register_value()
H A Dsvm_tests.c5 #include "msr.h"
329 static int get_msrpm_bit_nr(u32 msr) in get_msrpm_bit_nr() argument
333 switch (msr & ~SVM_MSRPM_OFFSET_MASK) { in get_msrpm_bit_nr()
348 (msr & SVM_MSRPM_OFFSET_MASK) * SVM_BITS_PER_MSR; in get_msrpm_bit_nr()
355 u32 msr; in __test_msr_intercept() local
357 for (msr = 0; msr <= 0xc0012000; msr++) { in __test_msr_intercept()
358 if (msr == 0xC0010131 /* MSR_SEV_STATUS */) { in __test_msr_intercept()
360 * Per section 15.34.10 "SEV_STATUS MSR" of AMD64 Architecture in __test_msr_intercept()
363 * SEV_STATUS MSR (C001_0131) is a non-interceptable MSR. in __test_msr_intercept()
369 * Test one MSR just before and after each range, but otherwise in __test_msr_intercept()
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H A Dhyperv_clock.c85 printf("drift on CPU %d, MSR value = %ld, acceptable [%ld, %ld]\n", i, in hv_clock_test()
92 printf("warp on CPU %d, MSR value = %ld prev MSR value = %ld!\n", i, in hv_clock_test()
186 "MSR value after enabling"); in main()
215 "MSR value after disabling"); in main()
H A Dpmu_lbr.c1 #include "x86/msr.h"
62 report_skip("Perfmon/Debug Capabilities MSR isn't supported."); in main()
H A Dsyscall.c1 /* msr tests */
5 #include "msr.h"
H A Dvmx_tests.c10 #include "msr.h"
292 u32 msr; in disable_intercept_for_x2apic_msrs() local
294 for (msr = APIC_BASE_MSR; in disable_intercept_for_x2apic_msrs()
295 msr < (APIC_BASE_MSR+0xff); in disable_intercept_for_x2apic_msrs()
296 msr += BITS_PER_LONG) { in disable_intercept_for_x2apic_msrs()
297 unsigned int word = msr / BITS_PER_LONG; in disable_intercept_for_x2apic_msrs()
1997 "VM entry MSR load"); in msr_switch_main()
2011 "VM exit MSR store"); in msr_switch_exit_handler()
2013 "VM exit MSR load"); in msr_switch_exit_handler()
2034 "VM entry MSR load: try to load FS_BASE"); in msr_switch_entry_failure()
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/kvm-unit-tests/lib/powerpc/asm/
H A Dprocessor.h43 uint64_t msr; in mfmsr() local
45 asm volatile ("mfmsr %[msr]" : [msr] "=r" (msr) :: "memory"); in mfmsr()
47 return msr; in mfmsr()
50 static inline void mtmsr(uint64_t msr) in mtmsr() argument
52 asm volatile ("mtmsrd %[msr]" :: [msr] "r" (msr) : "memory"); in mtmsr()
57 unsigned long msr; in local_irq_enable() local
65 : "=r"(msr) : "i"(MSR_EE): "memory"); in local_irq_enable()
70 unsigned long msr; in local_irq_disable() local
78 : "=r"(msr) : "r"(MSR_EE): "memory"); in local_irq_disable()
/kvm-unit-tests/powerpc/
H A Dinterrupts.c66 report(mfmsr() & MSR_ME, "pseries machine has MSR[ME]=1"); in test_mce()
72 report(mfmsr() & MSR_ME, "pseries is unable to change MSR[ME]"); in test_mce()
87 report(recorded_regs.msr & (1ULL << 21), "d-side MCE sets SRR1[42]"); in test_mce()
98 report(!(recorded_regs.msr & (1ULL << 21)), "i-side MCE clears SRR1[42]"); in test_mce()
130 uint64_t msr, tmp; in test_dseg_nommu() local
144 : "=r"(msr), "=r"(tmp) : "i"(MSR_DR): "memory"); in test_dseg_nommu()
194 report(recorded_regs.msr & (1ULL << 30), "SRR1 set correctly"); in test_mmu()
214 regs->msr &= ~MSR_EE; in dec_handler()
219 uint64_t msr; in test_dec() local
231 : "=r"(msr) : "r"(10000), "i"(MSR_EE): "memory"); in test_dec()
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H A Dtm.c59 uint64_t msr = 0; in enable_tm() local
61 asm volatile ("mfmsr %[msr]" : [msr] "=r" (msr)); in enable_tm()
63 msr |= (((uint64_t) 1) << 32); in enable_tm()
65 asm volatile ("mtmsrd %[msr]\n\t" in enable_tm()
66 "mfmsr %[msr]" : [msr] "+r" (msr)); in enable_tm()
68 return !!(msr & (((uint64_t) 1) << 32)); in enable_tm()
H A Demulator.c29 *data = regs->msr >> 16; in program_check_handler()
77 uint64_t msr; in test_64bit() local
81 asm("mfmsr %[msr]": [msr] "=r" (msr)); in test_64bit()
83 report(msr & 0x8000000000000000UL, "detected"); in test_64bit()
/kvm-unit-tests/arm/
H A Ddebug.c243 asm volatile("msr daifset, #8"); in reset_debug_state()
281 asm volatile("msr daifclr, #8"); in test_hw_bp()
298 "msr daifclr, #8; msr daifclr, #8; msr daifclr, #8; msr daifclr, #8\n" in test_hw_bp()
299 "msr daifclr, #8; msr daifclr, #8; msr daifclr, #8; msr daifclr, #8\n" in test_hw_bp()
300 "msr daifclr, #8; msr daifclr, #8; msr daifclr, #8; msr daifclr, #8\n" in test_hw_bp()
301 "msr daifclr, #8; msr daifclr, #8; msr daifclr, #8; msr daifclr, #8\n" in test_hw_bp()
328 asm volatile("msr daifclr, #8"); in test_wp()
343 asm volatile("msr daifclr, #8"); in test_wp()
371 asm volatile("msr daifclr, #8"); in test_ss()
378 "msr daifset, #8\n" in test_ss()
H A Dcstart64.S83 msr sctlr_el1, x4
87 msr spsel, x4
94 msr cpacr_el1, x4
191 msr cpacr_el1, x0
269 msr tcr_el1, x1
280 msr mair_el1, x1
283 msr ttbr0_el1, x0
291 msr sctlr_el1, x1
300 msr sctlr_el1, x0
321 msr vbar_el1, x4
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/kvm-unit-tests/lib/powerpc/
H A Dprocessor.c65 if (regs->msr & MSR_PR) in do_handle_exception()
70 printf("Unhandled CPU%d exception %#lx at NIA:0x%016lx MSR:0x%016lx\n", in do_handle_exception()
71 smp_processor_id(), regs->trap, regs->nip, regs->msr); in do_handle_exception()
127 * H_CEDE is called with MSR[EE] clear and enables it as part in sleep_tb()
150 static void rfid_msr(uint64_t msr) in rfid_msr() argument
163 : "=r"(tmp) : "r"(msr) : "lr"); in rfid_msr()
184 regs->msr &= ~(MSR_PR|MSR_EE); in usermode_sc_handler()
H A Dhandlers.c16 * Return with MSR[EE] disabled.
20 regs->msr &= ~(1UL << MSR_EE_BIT); in dec_handler_oneshot()
/kvm-unit-tests/lib/ppc64/asm/
H A Dptrace.h14 unsigned long msr; member
25 return regs->msr & SRR1_PREFIX; in regs_is_prefix()
/kvm-unit-tests/x86/efi/
H A DREADME.md25 ./x86/efi/run ./x86/msr.efi
31 EFI_UEFI=/path/to/OVMF.fd ./x86/efi/run ./x86/msr.efi
/kvm-unit-tests/
H A DREADME61 ./x86-run ./x86/msr.flat
75 QEMU=/tmp/qemu/x86_64-softmmu/qemu-system-x86_64 ./x86-run ./x86/msr.flat
80 ACCEL=kvm ./x86-run ./x86/msr.flat
H A D.gitignore21 /msr.out
H A DREADME.md61 ./x86-run ./x86/msr.flat
75 QEMU=/tmp/qemu/x86_64-softmmu/qemu-system-x86_64 ./x86-run ./x86/msr.flat
80 ACCEL=kvm ./x86-run ./x86/msr.flat
/kvm-unit-tests/lib/x86/
H A Dusermode.h4 #include "x86/msr.h"
H A Dfault_test.h4 #include "x86/msr.h"
/kvm-unit-tests/lib/arm64/asm/
H A Dprocessor.h63 asm volatile("msr daifclr, #2" : : : "memory"); in local_irq_enable()
68 asm volatile("msr daifset, #2" : : : "memory"); in local_irq_disable()

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