Lines Matching full:msr
5 #include "msr.h"
329 static int get_msrpm_bit_nr(u32 msr) in get_msrpm_bit_nr() argument
333 switch (msr & ~SVM_MSRPM_OFFSET_MASK) { in get_msrpm_bit_nr()
348 (msr & SVM_MSRPM_OFFSET_MASK) * SVM_BITS_PER_MSR; in get_msrpm_bit_nr()
355 u32 msr; in __test_msr_intercept() local
357 for (msr = 0; msr <= 0xc0012000; msr++) { in __test_msr_intercept()
358 if (msr == 0xC0010131 /* MSR_SEV_STATUS */) { in __test_msr_intercept()
360 * Per section 15.34.10 "SEV_STATUS MSR" of AMD64 Architecture in __test_msr_intercept()
363 * SEV_STATUS MSR (C001_0131) is a non-interceptable MSR. in __test_msr_intercept()
369 * Test one MSR just before and after each range, but otherwise in __test_msr_intercept()
370 * skips gaps between supported MSR ranges. in __test_msr_intercept()
372 if (msr == 0x2000 + 1) in __test_msr_intercept()
373 msr = 0xc0000000 - 1; in __test_msr_intercept()
374 else if (msr == 0xc0002000 + 1) in __test_msr_intercept()
375 msr = 0xc0010000 - 1; in __test_msr_intercept()
377 test->scratch = msr; in __test_msr_intercept()
382 vector = rdmsr_safe(msr, &val); in __test_msr_intercept()
385 msr, vector); in __test_msr_intercept()
386 else if (test->scratch != msr) in __test_msr_intercept()
388 msr, test->scratch); in __test_msr_intercept()
390 test->scratch = BIT_ULL(32) | msr; in __test_msr_intercept()
401 vector = wrmsr_safe(msr, arb_val); in __test_msr_intercept()
404 msr, vector); in __test_msr_intercept()
407 msr, test->scratch, arb_val); in __test_msr_intercept()
409 test->scratch = BIT_ULL(33) | msr; in __test_msr_intercept()
412 if (get_msrpm_bit_nr(msr) < 0) { in __test_msr_intercept()
413 report(msr == 0x2000 || in __test_msr_intercept()
414 msr == 0xc0000000 - 1 || msr == 0xc0002000 || in __test_msr_intercept()
415 msr == 0xc0010000 - 1 || msr == 0xc0012000, in __test_msr_intercept()
416 "MSR 0x%x not covered by an MSRPM range", msr); in __test_msr_intercept()
425 * is to verify interception, not MSR emulation/virtualization. in __test_msr_intercept()
428 (void)rdmsr_safe(msr, &val); in __test_msr_intercept()
431 msr, test->scratch); in __test_msr_intercept()
434 * Verify L1 and L2 see the same MSR value. Skip TSC to avoid in __test_msr_intercept()
437 if (val != exp && msr != MSR_IA32_TSC) in __test_msr_intercept()
439 msr, exp, val); in __test_msr_intercept()
441 test->scratch = BIT_ULL(34) | msr; in __test_msr_intercept()
445 (void)wrmsr_safe(msr, val); in __test_msr_intercept()
448 msr, test->scratch); in __test_msr_intercept()
450 test->scratch = BIT_ULL(35) | msr; in __test_msr_intercept()
482 u32 msr = test->scratch & -1u; in msr_intercept_finished() local
495 bit_nr = get_msrpm_bit_nr(msr); in msr_intercept_finished()
510 (void)rdmsr_safe(msr, &test->scratch); in msr_intercept_finished()
519 if (is_x2apic && msr >= 0x800 && msr <= 0x8ff) in msr_intercept_finished()
524 if (is_x2apic && msr >= 0x800 && msr <= 0x8ff) in msr_intercept_finished()
533 report_fail("Wanted MSR VM-Exit, got reason 0x%x", exit_code); in msr_intercept_finished()
542 * For RDMSR, test->scratch is set to the MSR index; in msr_intercept_finished()
543 * RCX holds the MSR index. in msr_intercept_finished()
544 * For WRMSR, test->scratch is set to the MSR value; in msr_intercept_finished()
545 * RDX holds the upper 32 bits of the MSR value, in msr_intercept_finished()
2503 * If the MSR or IOIO intercept table extends to a physical address that
2954 static u64 amd_get_lbr_rip(u32 msr) in amd_get_lbr_rip() argument
2956 return rdmsr(msr) & ~AMD_LBR_RECORD_MISPREDICT; in amd_get_lbr_rip()
3480 { "msr intercept check", default_supported, prepare_msr_intercept,