Lines Matching full:msr
10 #include "msr.h"
292 u32 msr; in disable_intercept_for_x2apic_msrs() local
294 for (msr = APIC_BASE_MSR; in disable_intercept_for_x2apic_msrs()
295 msr < (APIC_BASE_MSR+0xff); in disable_intercept_for_x2apic_msrs()
296 msr += BITS_PER_LONG) { in disable_intercept_for_x2apic_msrs()
297 unsigned int word = msr / BITS_PER_LONG; in disable_intercept_for_x2apic_msrs()
1997 "VM entry MSR load"); in msr_switch_main()
2011 "VM exit MSR store"); in msr_switch_exit_handler()
2013 "VM exit MSR load"); in msr_switch_exit_handler()
2034 "VM entry MSR load: try to load FS_BASE"); in msr_switch_entry_failure()
3442 static void test_rsvd_ctl_bit_value(const char *name, union vmx_ctrl_msr msr, in test_rsvd_ctl_bit_value() argument
3450 if (msr.set & mask) in test_rsvd_ctl_bit_value()
3451 TEST_ASSERT(msr.clr & mask); in test_rsvd_ctl_bit_value()
3458 if (val && (msr.clr & mask) && !(msr.set & mask)) in test_rsvd_ctl_bit_value()
3466 vmcs_write(encoding, msr.set | mask); in test_rsvd_ctl_bit_value()
3467 expected = (msr.clr & mask); in test_rsvd_ctl_bit_value()
3469 vmcs_write(encoding, msr.set & ~mask); in test_rsvd_ctl_bit_value()
3470 expected = !(msr.set & mask); in test_rsvd_ctl_bit_value()
3482 * allowed bit settings from the corresponding VMX capability MSR.
3484 static void test_rsvd_ctl_bit(const char *name, union vmx_ctrl_msr msr, in test_rsvd_ctl_bit() argument
3487 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 0); in test_rsvd_ctl_bit()
3488 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 1); in test_rsvd_ctl_bit()
3581 * should read the VMX capability MSR IA32_VMX_MISC to determine the
3729 * If the "use MSR bitmaps" VM-execution control is 1, bits 11:0 of
3730 * the MSR-bitmap address must be 0. The address should not set any
3737 "MSR bitmap", "Use MSR bitmaps", in test_msr_bitmap()
4708 * processor as indicated in the IA32_VMX_EPT_VPID_CAP MSR.
4712 * 0 if bit 21 of the IA32_VMX_EPT_VPID_CAP MSR is read as 0,
5334 * The following checks are performed for the VM-entry MSR-load address if
5335 * the VM-entry MSR-load count field is non-zero:
5337 * - The lower 4 bits of the VM-entry MSR-load address must be 0.
5341 * - The address of the last byte in the VM-entry MSR-load area
5343 * width. The address of this last byte is VM-entry MSR-load address
5344 * + (MSR count * 16) - 1. (The arithmetic used for the computation
5360 /* Check first 4 bits of VM-entry MSR-load address */ in test_entry_msr_load()
5364 report_prefix_pushf("VM-entry MSR-load addr [4:0] %lx", in test_entry_msr_load()
5373 test_vmcs_addr_values("VM-entry-MSR-load address", in test_entry_msr_load()
5378 * Check last byte of VM-entry MSR-load address in test_entry_msr_load()
5401 u32 msr; member
5416 obs = rdmsr(data->msr); in guest_state_test_main()
5460 * The following checks are performed for the VM-exit MSR-store address if
5461 * the VM-exit MSR-store count field is non-zero:
5463 * - The lower 4 bits of the VM-exit MSR-store address must be 0.
5467 * - The address of the last byte in the VM-exit MSR-store area
5469 * width. The address of this last byte is VM-exit MSR-store address
5470 * + (MSR count * 16) - 1. (The arithmetic used for the computation
5488 /* Check first 4 bits of VM-exit MSR-store address */ in test_exit_msr_store()
5492 report_prefix_pushf("VM-exit MSR-store addr [4:0] %lx", in test_exit_msr_store()
5501 test_vmcs_addr_values("VM-exit-MSR-store address", in test_exit_msr_store()
5506 * Check last byte of VM-exit MSR-store address in test_exit_msr_store()
6439 * - x2APIC MSR intercepts disabled
6584 * Disable "Virtualize x2APIC mode", disable x2APIC MSR intercepts, and
6867 int msr; in configure_virt_x2apic_mode_test() local
6873 /* virt_x2apic_mode_test() checks for MSR bitmaps support */ in configure_virt_x2apic_mode_test()
6892 /* x2APIC MSR intercepts are usually off for "Virtualize x2APIC mode" */ in configure_virt_x2apic_mode_test()
6893 for (msr = 0x800; msr <= 0x8ff; msr++) { in configure_virt_x2apic_mode_test()
6895 clear_bit(msr, msr_bitmap_page + 0x000); in configure_virt_x2apic_mode_test()
6896 clear_bit(msr, msr_bitmap_page + 0x800); in configure_virt_x2apic_mode_test()
6898 set_bit(msr, msr_bitmap_page + 0x000); in configure_virt_x2apic_mode_test()
6899 set_bit(msr, msr_bitmap_page + 0x800); in configure_virt_x2apic_mode_test()
6928 * MSR bitmaps. Previously, an L1 could get at L0's x2APIC MSRs by in virt_x2apic_mode_test()
6929 * writing the IA32_SPEC_CTRL MSR or the IA32_PRED_CMD MSRs. KVM would in virt_x2apic_mode_test()
6930 * then proceed to manipulate the MSR bitmaps, as if VMCS12 had the in virt_x2apic_mode_test()
6939 * - "MSR-bitmap address", indicated by "use MSR bitmaps" in virt_x2apic_mode_test()
6945 report_skip("%s : \"Use MSR bitmaps\" exec control not supported", __func__); in virt_x2apic_mode_test()
7242 * IA32_EFER MSR must be 0 in the field for that register. In addition,
7257 * IA32_EFER MSR must be 0 in the field for that register. In addition,
7353 * for the IA32_PAT MSR must be one that could be written by WRMSR
7429 obs = rdmsr(data->msr); in test_pgc_vmlaunch()
7467 data->msr = MSR_CORE_PERF_GLOBAL_CTRL; in test_perf_global_ctrl()
7520 report_skip("%s : \"IA32_PERF_GLOBAL_CTRL\" MSR not supported", __func__); in test_load_host_perf_global_ctrl()
7537 report_skip("%s : \"IA32_PERF_GLOBAL_CTRL\" MSR not supported", __func__); in test_load_guest_perf_global_ctrl()
7834 * for the IA32_PAT MSR must be one that could be written by WRMSR
7858 * checks are performed on the field for the IA32_BNDCFGS MSR:
7860 * - Bits reserved in the IA32_BNDCFGS MSR must be 0.
8853 * This test ensures that when IA32_TSC is in the VM-exit MSR-store
8883 "IA32_TSC value saved in the VM-exit MSR-store list (%lu) is in range [%lu, %lu]", in vmx_store_tsc_test()
10314 * and the IA32_TIME_STAMP_COUNTER MSR value stored in the VMCS12
10315 * VM-exit MSR-store list when taking a VM-exit on the instruction
10384 * Set up the VMCS12 VM-exit MSR-store list to store just one in rdtsc_vmexit_diff_test()
10385 * MSR: IA32_TIME_STAMP_COUNTER. Note that the value stored is in rdtsc_vmexit_diff_test()
10431 report_fail("Invalid MSR load"); in invalid_msr_main()
10436 report_fail("Invalid MSR load"); in invalid_msr_exit_handler()
10444 result->exit_reason.basic == VMX_FAIL_MSR, "Invalid MSR load"); in invalid_msr_entry_failure()
10449 * The max number of MSRs in an atomic switch MSR list is:
10453 * 4-byte MSR index + 4 bytes reserved + 8-byte data = 16 bytes
10494 /* Exceeding the max MSR list size at exit triggers KVM to abort. */ in atomic_switch_msrs_test()
10500 * Check for the IA32_TSC MSR, in atomic_switch_msrs_test()
10501 * available with the "TSC flag" and used to populate the MSR lists. in atomic_switch_msrs_test()
10511 /* Setup atomic MSR switch lists. */ in atomic_switch_msrs_test()
10539 test_guest_state("Invalid MSR Load Count", true, count, in atomic_switch_msrs_test()
10819 * an MSR, and for indirect writes via loads from VMCS fields on VM-Exit.
11407 { "MSR switch", msr_switch_init, msr_switch_main,
11480 /* Atomic MSR switch tests. */