Home
last modified time | relevance | path

Searched +full:keep +full:- +full:pll +full:- +full:enabled (Results 1 – 25 of 107) sorted by relevance

12345

/linux-5.10/Documentation/devicetree/bindings/net/
Dqca,ar803x.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
18 - $ref: ethernet-phy.yaml#
21 qca,clk-out-frequency:
26 qca,clk-out-strength:
31 qca,keep-pll-enabled:
[all …]
/linux-5.10/drivers/clk/meson/
Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0
11 * In the most basic form, a Meson PLL is composed as follows:
13 * PLL
14 * +--------------------------------+
16 * | +--+ |
17 * in >>-----[ /N ]--->| | +-----+ |
18 * | | |------| DCO |---->> out
19 * | +--------->| | +--v--+ |
20 * | | +--+ | |
22 * | +--[ *(M + (F/Fmax) ]<--+ |
[all …]
/linux-5.10/drivers/net/phy/
Dat803x.c1 // SPDX-License-Identifier: GPL-2.0+
22 #include <dt-bindings/net/qca-ar803x.h>
86 #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/
99 /* AT803x supports either the XTAL input pad, an internal PLL or the
101 * is only used for 25 MHz output, all other frequencies need the PLL.
105 * By default the PLL is only enabled if there is a link. Otherwise
106 * the PHY will go into low power state and disabled the PLL. You can
107 * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always
108 * enabled.
122 * but doesn't support choosing between XTAL/PLL and DSP.
[all …]
/linux-5.10/drivers/gpu/drm/bridge/
Dtc358768.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com
26 /* Global (16-bit addressable) */
43 /* Debug (16-bit addressable) */
49 /* TX PHY (32-bit addressable) */
61 /* TX PPI (32-bit addressable) */
77 /* TX CTRL (32-bit addressable) */
98 /* DSITX CTRL (16-bit addressable) */
141 int enabled; member
151 /* Parameters for PLL programming */
[all …]
/linux-5.10/drivers/gpu/drm/radeon/
Dradeon_legacy_crtc.c2 * Copyright 2007-8 Advanced Micro Devices, Inc.
40 struct drm_device *dev = crtc->dev; in radeon_overscan_setup()
41 struct radeon_device *rdev = dev->dev_private; in radeon_overscan_setup()
44 WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup()
45 WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup()
46 WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup()
52 struct drm_device *dev = crtc->dev; in radeon_legacy_rmx_mode_set()
53 struct radeon_device *rdev = dev->dev_private; in radeon_legacy_rmx_mode_set()
55 int xres = mode->hdisplay; in radeon_legacy_rmx_mode_set()
56 int yres = mode->vdisplay; in radeon_legacy_rmx_mode_set()
[all …]
/linux-5.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/
Ddce_clk_mgr.c2 * Copyright 2012-16 Advanced Micro Devices, Inc.
47 (clk_mgr->regs->reg)
51 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
68 /* ClocksStateInvalid - should not be used */
70 /* ClocksStateUltraLow - not expected to be used for DCE 8.0 */
88 * (did - DENTIST_BASE_DID_1); in dentist_get_divider_from_did()
91 * (did - DENTIST_BASE_DID_2); in dentist_get_divider_from_did()
94 * (did - DENTIST_BASE_DID_3); in dentist_get_divider_from_did()
97 * (did - DENTIST_BASE_DID_4); in dentist_get_divider_from_did()
104 -if SS enabled on DP Ref clock and HW de-spreading enabled with SW
[all …]
/linux-5.10/drivers/phy/broadcom/
Dphy-brcm-usb-init.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * phy-brcm-usb-init.c - Broadcom USB Phy chip specific init functions
5 * Copyright (C) 2014-2017 Broadcom
16 #include "phy-brcm-usb-init.h"
133 (params->usb_reg_bits_map[USB_CTRL_##reg##_##field##_SELECTOR])
403 mask = params->usb_reg_bits_map[field]; in usb_ctrl_unset_family()
404 brcm_usb_ctrl_unset(params->regs[BRCM_REGS_CTRL] + reg_offset, mask); in usb_ctrl_unset_family()
413 mask = params->usb_reg_bits_map[field]; in usb_ctrl_set_family()
414 brcm_usb_ctrl_set(params->regs[BRCM_REGS_CTRL] + reg_offset, mask); in usb_ctrl_set_family()
460 /* reset USB 2.0 PLL */ in brcmusb_usb_phy_ldo_fix()
[all …]
/linux-5.10/drivers/net/wireless/broadcom/b43/
Db43.h1 /* SPDX-License-Identifier: GPL-2.0 */
61 /* 32-bit DMA */
68 /* 64-bit DMA */
203 #define B43_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
209 #define B43_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
211 #define B43_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
212 #define B43_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */
234 #define B43_SHM_AUTOINC_R 0x0200 /* Auto-increment address on read */
235 #define B43_SHM_AUTOINC_W 0x0100 /* Auto-increment address on write */
330 #define B43_SHM_SH_SPUWKUP 0x0094 /* pre-wakeup for synth PU in us */
[all …]
/linux-5.10/drivers/i2c/busses/
Di2c-mlxbf.c1 // SPDX-License-Identifier: GPL-2.0
53 * Note that the following SMBus, CAUSE, GPIO and PLL register addresses
55 * memory-mapped region whose addresses are specified in either the DT or
65 /* Reference clock for Bluefield - 156 MHz. */
68 /* Constant used to determine the PLL frequency. */
71 /* PLL registers. */
85 * as interrupt enabled bits.
122 * as interrupt enabled bits.
150 * SMBUS GW0 -> bits[26:25]
151 * SMBUS GW1 -> bits[28:27]
[all …]
/linux-5.10/drivers/gpu/drm/i915/display/
Dintel_display.c2 * Copyright © 2006-2007 Intel Corporation
29 #include <linux/intel-iommu.h>
32 #include <linux/dma-resv.h>
208 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != in vlv_get_cck_clock()
222 if (dev_priv->hpll_freq == 0) in vlv_get_cck_clock_hpll()
223 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); in vlv_get_cck_clock_hpll()
225 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); in vlv_get_cck_clock_hpll()
237 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", in intel_update_czclk()
240 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", in intel_update_czclk()
241 dev_priv->czclk_freq); in intel_update_czclk()
[all …]
Dintel_display_types.h3 * Copyright (c) 2007-2008 Intel Corporation
44 #include <media/cec-notifier.h>
56 /* these are outputs from the chip - integrated only
74 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
96 /* for each plane in the rotated GTT view for no-CCS formats */
181 * the encoder is active. If the encoder is enabled it also set the pipe
185 * state. This must be called _after_ display->get_pipe_config has
186 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
218 bool enabled; member
257 * and the bus-specific code. What that means is that HDCP over HDMI differs
[all …]
/linux-5.10/include/linux/bcma/
Dbcma_driver_chipcommon.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 #define BCMA_CC_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
33 #define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */
48 #define BCMA_CC_CAP_64BIT 0x08000000 /* 64-bit Backplane */
102 #define BCMA_CC_CHIPST_4706_PKG_OPTION BIT(0) /* 0: full-featured package 1: low-cost package */
104 #define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
153 #define BCMA_CC_FLASHCTL_ST_DP 0x00b9 /* Deep Power-down */
155 #define BCMA_CC_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */
156 #define BCMA_CC_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
234 #define BCMA_CC_SLOWCLKCTL_LPOPD 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled…
[all …]
/linux-5.10/drivers/gpu/drm/rcar-du/
Drcar_lvds.c1 // SPDX-License-Identifier: GPL-2.0
3 * rcar_lvds.c -- R-Car LVDS Encoder
5 * Copyright (C) 2013-2018 Renesas Electronics Corporation
34 /* Keep in sync with the LVDCR0.LVMD hardware register values. */
50 #define RCAR_LVDS_QUIRK_EXT_PLL BIT(3) /* Has extended PLL */
51 #define RCAR_LVDS_QUIRK_DUAL_LINK BIT(4) /* Supports dual-link operation */
88 iowrite32(data, lvds->mmio + reg); in rcar_lvds_write()
91 /* -----------------------------------------------------------------------------
99 return drm_panel_get_modes(lvds->panel, connector); in rcar_lvds_connector_get_modes()
111 if (!conn_state->crtc) in rcar_lvds_connector_atomic_check()
[all …]
/linux-5.10/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
Dmain.h48 * Usage example, e.g. a three-bit field (bits 4-6):
52 * regval = R_REG(osh, &regs->regfoo);
55 * W_REG(osh, &regs->regfoo, regval);
58 (((unsigned)1 << (width)) - 1)
67 /* max # supported core revisions (0 .. MAXCOREREV - 1) */
70 /* Double check that unsupported cores are not enabled */
76 #define BRCMS_SHORTSLOT_AUTO -1 /* Driver will manage Shortslot setting */
91 #define TXFID_QUEUE_MASK 0x0007 /* Bits 0-2 */
92 #define TXFID_SEQ_MASK 0x7FE0 /* Bits 5-15 */
132 /* PLL requests */
[all …]
/linux-5.10/arch/powerpc/platforms/512x/
Dclock-commonclk.c1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <linux/clk-provider.h>
21 #include <dt-bindings/clock/mpc512x-clock.h>
25 /* helpers to keep the MCLK intermediates "somewhere" in our table */
88 * NFC IP block, output clocks, system PLL status query, different CPMF
89 * interpretation, no CFM, different fourth PSC/CAN mux0 input -- yet
292 val &= (1 << len) - 1; in get_bit_field()
296 /* get the SPMF and translate it into the "sys pll" multiplier */
305 spmf = get_bit_field(&clkregs->spmr, 24, 4); in get_spmf_mult()
326 divcode = get_bit_field(&clkregs->scfr2, 26, 6); in get_sys_div_x2()
[all …]
/linux-5.10/include/linux/ssb/
Dssb_driver_chipcommon.h1 /* SPDX-License-Identifier: GPL-2.0-only */
30 #define SSB_CHIPCO_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
37 #define SSB_CHIPCO_CAP_PLLT 0x00038000 /* PLL Type */
52 #define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */
161 …e SSB_CHIPCO_SLOWCLKCTL_LPOPD 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
163 …CLKCTL_IPLL 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable reque…
260 /** PMU PLL registers */
262 /* PMU rev 0 PLL registers */
276 /* PMU rev 1 PLL registers */
308 /* BCM4312 PLL resource numbers. */
[all …]
/linux-5.10/arch/arm/boot/dts/
Dtegra124-nyan.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
13 stdout-path = "serial0:115200n8";
19 * missing a unit-address. However, the bootloader on these Chromebook
21 * Adding the unit-address causes the bootloader to create a /memory
33 /delete-node/ memory@80000000;
39 vdd-supply = <&vdd_3v3_hdmi>;
40 pll-supply = <&vdd_hdmi_pll>;
41 hdmi-supply = <&vdd_5v0_hdmi>;
43 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
[all …]
/linux-5.10/sound/soc/codecs/
Dda7219-aad.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * da7219-aad.c - Dialog DA7219 ALSA SoC AAD Driver
24 #include "da7219-aad.h"
35 da7219->aad->jack = jack; in da7219_aad_jack_det()
36 da7219->aad->jack_inserted = false; in da7219_aad_jack_det()
56 struct snd_soc_component *component = da7219_aad->component; in da7219_aad_btn_det_work()
84 dev_warn(component->dev, "Mic bias status check timed out"); in da7219_aad_btn_det_work()
86 da7219->micbias_on_event = true; in da7219_aad_btn_det_work()
92 if (da7219_aad->micbias_pulse_lvl && da7219_aad->micbias_pulse_time) { in da7219_aad_btn_det_work()
97 da7219_aad->micbias_pulse_lvl); in da7219_aad_btn_det_work()
[all …]
/linux-5.10/drivers/net/wireless/broadcom/b43legacy/
Db43legacy.h1 /* SPDX-License-Identifier: GPL-2.0 */
59 /* 32-bit DMA */
66 /* 64-bit DMA */
119 #define B43legacy_SHM_AUTOINC_R 0x0200 /* Read Auto-increment */
120 #define B43legacy_SHM_AUTOINC_W 0x0100 /* Write Auto-increment */
153 #define B43legacy_SHM_SH_SPUWKUP 0x0094 /* pre-wakeup for synth PU in us */
154 #define B43legacy_SHM_SH_PRETBTT 0x0096 /* pre-TBTT in us */
163 #define B43legacy_HF_SYMW 0x00000002 /* G-PHY SYM workaround */
164 #define B43legacy_HF_GDCW 0x00000020 /* G-PHY DV cancel filter */
192 #define B43legacy_MACCTL_ENABLED 0x00000001 /* MAC Enabled */
[all …]
/linux-5.10/drivers/video/fbdev/intelfb/
Dintelfbhw.c13 * the i810/i830 XFree86 driver. The HW-specific code is covered here
73 switch (pdev->device) { in intelfbhw_get_chipset()
75 dinfo->name = "Intel(R) 830M"; in intelfbhw_get_chipset()
76 dinfo->chipset = INTEL_830M; in intelfbhw_get_chipset()
77 dinfo->mobile = 1; in intelfbhw_get_chipset()
78 dinfo->pll_index = PLLS_I8xx; in intelfbhw_get_chipset()
81 dinfo->name = "Intel(R) 845G"; in intelfbhw_get_chipset()
82 dinfo->chipset = INTEL_845G; in intelfbhw_get_chipset()
83 dinfo->mobile = 0; in intelfbhw_get_chipset()
84 dinfo->pll_index = PLLS_I8xx; in intelfbhw_get_chipset()
[all …]
/linux-5.10/drivers/usb/host/
Dehci-pci.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (c) 2000-2004 by David Brownell
15 #include "pci-quirks.h"
19 static const char hcd_name[] = "ehci-pci";
24 /*-------------------------------------------------------------------------*/
28 return pdev->vendor == PCI_VENDOR_ID_INTEL && in is_intel_quark_x1000()
29 pdev->device == PCI_DEVICE_ID_INTEL_QUARK_X1000_SOC; in is_intel_quark_x1000()
59 /* called after powerup, by probe or system-pm "wakeup" */
68 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ in ehci_pci_reinit()
80 ehci->regs->intel_quark_x1000_insnreg01); in ehci_pci_reinit()
[all …]
/linux-5.10/drivers/net/ethernet/sun/
Dsungem.h1 /* SPDX-License-Identifier: GPL-2.0 */
39 * This auto-clearing does not occur when the alias at GREG_STAT2
69 * signalled to the cpu. GREG_IACK can be used to clear specific top-level
130 * This 13-bit register is programmed by the driver to hold the descriptor
136 * This 13-bit register is updated by GEM to hold to descriptor entry index
171 * them later. -DaveM
220 #define RXDMA_CFG_RINGSZ_32 0x00000000 /* - 32 entries */
221 #define RXDMA_CFG_RINGSZ_64 0x00000002 /* - 64 entries */
222 #define RXDMA_CFG_RINGSZ_128 0x00000004 /* - 128 entries */
223 #define RXDMA_CFG_RINGSZ_256 0x00000006 /* - 256 entries */
[all …]
/linux-5.10/sound/soc/intel/boards/
Dbytcr_rt5640.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * byt_cr_dpcm_rt5640.c - ASoc Machine driver for Intel Byt CR platform
27 #include <sound/soc-acpi.h>
28 #include <dt-bindings/sound/rt5640.h>
30 #include "../atom/sst-atom-controls.h"
31 #include "../common/soc-intel-quirks.h"
68 #define BYT_RT5640_DIFF_MIC BIT(18) /* default is single-ended */
82 /* in-diff or dmic-pin + jdsrc + ovcd-th + -sf + jd-inv + terminating entry */
92 static int quirk_override = -1;
94 MODULE_PARM_DESC(quirk, "Board-specific quirk override");
[all …]
/linux-5.10/drivers/gpu/drm/amd/display/dc/dce/
Ddce_clk_mgr.c2 * Copyright 2012-16 Advanced Micro Devices, Inc.
39 (clk_mgr_dce->regs->reg)
43 clk_mgr_dce->clk_mgr_shift->field_name, clk_mgr_dce->clk_mgr_mask->field_name
46 clk_mgr_dce->base.ctx
48 clk_mgr->ctx->logger
52 /* ClocksStateInvalid - should not be used */
54 /* ClocksStateUltraLow - not expected to be used for DCE 8.0 */
64 /*ClocksStateInvalid - should not be used*/
66 /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
76 /*ClocksStateInvalid - should not be used*/
[all …]
Ddce_clock_source.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
43 (clk_src->regs->reg)
46 clk_src->base.ctx
52 clk_src->cs_shift->field_name, clk_src->cs_mask->field_name
74 ss_parm = clk_src->dvi_ss_params; in get_ss_data_entry()
75 entrys_num = clk_src->dvi_ss_params_cnt; in get_ss_data_entry()
79 ss_parm = clk_src->hdmi_ss_params; in get_ss_data_entry()
80 entrys_num = clk_src->hdmi_ss_params_cnt; in get_ss_data_entry()
84 ss_parm = clk_src->lvds_ss_params; in get_ss_data_entry()
85 entrys_num = clk_src->lvds_ss_params_cnt; in get_ss_data_entry()
[all …]

12345