linux/ssb/ssb_driver_chipcommon.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
30 #define  SSB_CHIPCO_CAP_UARTGPIO	0x00000020	/* UARTs on GPIO 15-12 */
37 #define  SSB_CHIPCO_CAP_PLLT		0x00038000	/* PLL Type */
52 #define  SSB_CHIPCO_CAP_64BIT		0x08000000	/* 64-bit Backplane */
161 …e  SSB_CHIPCO_SLOWCLKCTL_LPOPD	0x00000400	/* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
163 …CLKCTL_IPLL	0x00001000	/* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable reque…
260 /** PMU PLL registers */
262 /* PMU rev 0 PLL registers */
276 /* PMU rev 1 PLL registers */
308 /* BCM4312 PLL resource numbers. */
325 /* BCM4325 PLL resource numbers. */
349 /* BCM4328 PLL resource numbers. */
371 /* BCM5354 PLL resource numbers. */
395 /** Chip specific Chip-Status register contents. */
410 /** Macros to determine SPROM presence based on Chip-Status register. */
430 #define	SSB_CHIPCO_CLK_PLLC		0x000F0000	/* pll control */
444 #define	SSB_CHIPCO_CLK_F6_3		0x03		/* 6-bit fields like */
450 #define	SSB_CHIPCO_CLK_F5_BIAS		5		/* 5-bit fields get this added */
474 #define SSB_CHIPCO_CLK_BASE2		12500000	/* Alternate crystal on some PLL's */
495 /** Flash-specific control/status values */
506 #define SSB_CHIPCO_FLASHCTL_ST_DP	0x00B9		/* Deep Power-down */
508 #define SSB_CHIPCO_FLASHCTL_ST_CSA	0x1000		/* Keep chip select asserted */
509 #define SSB_CHIPCO_FLASHCTL_ST_SSE	0x0220		/* Sub-sector Erase */
556 #define	SSB_CHIPCO_OTP_SWLIM_OFF	(-8)
561 #define	SSB_CHIPCO_OTP_BOUNDARY_OFF	(-4)
562 #define	SSB_CHIPCO_OTP_HWSIGN_OFF	(-3)
563 #define	SSB_CHIPCO_OTP_SWSIGN_OFF	(-2)
564 #define	SSB_CHIPCO_OTP_CIDSIGN_OFF	(-1)
580  * Check availability with ((struct ssb_chipcommon)->capabilities & SSB_CHIPCO_CAP_PMU)
601 	return (cc->dev != NULL);  in ssb_chipco_available()
605 #define chipco_read32(cc, offset)	ssb_read32((cc)->dev, offset)
606 #define chipco_write32(cc, offset, val)	ssb_write32((cc)->dev, offset, val)